static void gfar_configure_serdes(struct gfar_private *priv)
{
gfar_local_mdio_write(priv->phyregs_sgmii,
in_be32(priv->regs + GFAR_TBIPA_OFFSET), GFAR_TBI_ANA,
priv->tbiana);
gfar_local_mdio_write(priv->phyregs_sgmii,
in_be32(priv->regs + GFAR_TBIPA_OFFSET),
GFAR_TBI_TBICON, GFAR_TBICON_CLK_SELECT);
gfar_local_mdio_write(priv->phyregs_sgmii,
in_be32(priv->regs + GFAR_TBIPA_OFFSET), GFAR_TBI_CR,
priv->tbicr);
}
/* Reset the internal and external PHYs. */
static void gfar_init_phy(struct eth_device *dev)
{
struct gfar_private *priv = dev->priv;
void __iomem *regs = priv->regs;
uint64_t start;
/* Assign a Physical address to the TBI */
out_be32(regs + GFAR_TBIPA_OFFSET, GFAR_TBIPA_VALUE);
/* Reset MII (due to new addresses) */
out_be32(priv->phyregs + GFAR_MIIMCFG_OFFSET, GFAR_MIIMCFG_RESET);
out_be32(priv->phyregs + GFAR_MIIMCFG_OFFSET, GFAR_MIIMCFG_INIT_VALUE);
start = get_time_ns();
while (!is_timeout(start, 10 * MSECOND)) {
if (!(in_be32(priv->phyregs + GFAR_MIIMMIND_OFFSET) &
GFAR_MIIMIND_BUSY))
break;
}
gfar_local_mdio_write(priv->phyregs, priv->phyaddr, GFAR_MIIM_CR,
GFAR_MIIM_CR_RST);
start = get_time_ns();
while (!is_timeout(start, 10 * MSECOND)) {
if (!(gfar_local_mdio_read(priv->phyregs, priv->phyaddr,
GFAR_MIIM_CR) & GFAR_MIIM_CR_RST))
break;
}
if (in_be32(regs + GFAR_ECNTRL_OFFSET) & GFAR_ECNTRL_SGMII_MODE)
gfar_configure_serdes(priv);
}
/* Write value to the PHY at mii_id at register regnum,
* on the bus, waiting until the write is done before returning.
* All PHY configuration is done through the TSEC1 MIIM regs */
int gfar_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value)
{
struct gfar_mii __iomem *regs = (void __iomem *)bus->priv;
/* Write to the local MII regs */
return(gfar_local_mdio_write(regs, mii_id, regnum, value));
}
/* Write a MII PHY register. */
static int gfar_miiphy_write(struct mii_bus *bus, int addr, int reg,
u16 value)
{
struct gfar_phy *phy = bus->priv;
unsigned short val = value;
int ret;
ret = gfar_local_mdio_write(phy->regs, addr, reg, val);
if (ret)
dev_err(phy->dev, "Can't write PHY at address %d\n", addr);
return 0;
}
/* Write a MII PHY register. */
static int gfar_miiphy_write(struct mii_bus *bus, int addr, int reg,
u16 value)
{
struct device_d *dev = bus->parent;
struct gfar_private *priv = bus->priv;
unsigned short val = value;
int ret;
ret = gfar_local_mdio_write(priv->phyregs, addr, reg, val);
if (ret)
dev_err(dev, "Can't write PHY at address %d\n", addr);
return 0;
}
/* Reset the external PHYs. */
static void gfar_init_phy(struct eth_device *dev)
{
struct gfar_private *priv = dev->priv;
struct gfar_phy *phy = priv->gfar_mdio;
void __iomem *regs = priv->regs;
uint64_t start;
gfar_local_mdio_write(phy->regs, priv->phyaddr, GFAR_MIIM_CR,
GFAR_MIIM_CR_RST);
start = get_time_ns();
while (!is_timeout(start, 10 * MSECOND)) {
if (!(gfar_local_mdio_read(phy->regs, priv->phyaddr,
GFAR_MIIM_CR) & GFAR_MIIM_CR_RST))
break;
}
if (in_be32(regs + GFAR_ECNTRL_OFFSET) & GFAR_ECNTRL_SGMII_MODE)
gfar_configure_serdes(priv);
}
