/*
* Note: assumes caller has acquired <msm_rpm_irq_lock>.
*/
static void msm_rpm_busy_wait_for_request_completion(
bool allow_async_completion)
{
int rc;
do {
while (!gic_is_irq_pending(msm_rpm_data.irq_ack) &&
msm_rpm_request) {
if (allow_async_completion)
spin_unlock(&msm_rpm_irq_lock);
if (gic_is_irq_pending(msm_rpm_data.irq_err))
msm_rpm_err_fatal();
gic_clear_irq_pending(msm_rpm_data.irq_err);
udelay(1);
if (allow_async_completion)
spin_lock(&msm_rpm_irq_lock);
}
if (!msm_rpm_request)
break;
rc = msm_rpm_process_ack_interrupt();
gic_clear_irq_pending(msm_rpm_data.irq_ack);
} while (rc);
}
/* Called from the FIQ asm handler */
void msm7k_fiq_handler(void)
{
struct irq_data *d;
struct irq_chip *c;
struct pt_regs context_regs;
pr_info("Fiq is received %s\n", __func__);
fiq_counter++;
d = irq_get_irq_data(MSM8625_INT_A9_M2A_2);
c = irq_data_get_irq_chip(d);
c->irq_mask(d);
local_irq_disable();
/* Clear the IRQ from the ENABLE_SET */
gic_clear_irq_pending(MSM8625_INT_A9_M2A_2);
local_irq_enable();
flush_cache_all();
outer_flush_all();
pr_err("%s msm_dump_cpu_ctx usr_r0:0x%x", __func__, msm_dump_cpu_ctx.usr_r0);
pr_err("%s msm_dump_cpu_ctx usr_r0:0x%x usr_r1:0x%x usr_r2:0x%x usr_r3:0x%x usr_r4:0x%x usr_r5:0x%x usr_r6:0x%x usr_r7:0x%x usr_r8:0x%x usr_r9:0x%x usr_r10:0x%x usr_r11:0x%x usr_r12:0x%x usr_r13:0x%x usr_r14:0x%x irq_spsr:0x%x irq_r13:0x%x irq_r14:0x%x svc_spsr:0x%x svc_r13:0x%x svc_r14:0x%x abt_spsr:0x%x abt_r13:0x%x abt_r14:0x%x und_spsr:0x%x und_r13:0x%x und_r14:0x%x fiq_spsr:0x%x fiq_r8:0x%x fiq_r9:0x%x fiq_r10:0x%x fiq_r11:0x%x fiq_r12:0x%x fiq_r13:0x%x fiq_r14:0x%x\n",__func__, msm_dump_cpu_ctx.usr_r0,msm_dump_cpu_ctx.usr_r1,msm_dump_cpu_ctx.usr_r2,msm_dump_cpu_ctx.usr_r3, msm_dump_cpu_ctx.usr_r4, msm_dump_cpu_ctx.usr_r5, msm_dump_cpu_ctx.usr_r6, msm_dump_cpu_ctx.usr_r7, msm_dump_cpu_ctx.usr_r8, msm_dump_cpu_ctx.usr_r9, msm_dump_cpu_ctx.usr_r10, msm_dump_cpu_ctx.usr_r11, msm_dump_cpu_ctx.usr_r12, msm_dump_cpu_ctx.usr_r13, msm_dump_cpu_ctx.usr_r14, msm_dump_cpu_ctx.irq_spsr, msm_dump_cpu_ctx.irq_r13, msm_dump_cpu_ctx.irq_r14, msm_dump_cpu_ctx.svc_spsr, msm_dump_cpu_ctx.svc_r13, msm_dump_cpu_ctx.svc_r14, msm_dump_cpu_ctx.abt_spsr,msm_dump_cpu_ctx.abt_r13, msm_dump_cpu_ctx.abt_r14, msm_dump_cpu_ctx.und_spsr,msm_dump_cpu_ctx.und_r13, msm_dump_cpu_ctx.und_r14, msm_dump_cpu_ctx.fiq_spsr,msm_dump_cpu_ctx.fiq_r8, msm_dump_cpu_ctx.fiq_r9, msm_dump_cpu_ctx.fiq_r10, msm_dump_cpu_ctx.fiq_r11, msm_dump_cpu_ctx.fiq_r12, msm_dump_cpu_ctx.fiq_r13, msm_dump_cpu_ctx.fiq_r14);
context_regs.ARM_sp = msm_dump_cpu_ctx.svc_r13;
context_regs.ARM_lr = msm_dump_cpu_ctx.svc_r14;
context_regs.ARM_fp = msm_dump_cpu_ctx.usr_r11; //for the svc r11 is the same with usr r11
context_regs.ARM_pc = msm_dump_cpu_ctx.svc_r14;
//dump_stack();
unwind_backtrace(&context_regs, current);
#ifdef CONFIG_SMP
trigger_all_cpu_backtrace();
#endif
return;
}
static void clear_pending_spi(unsigned int irq)
{
struct irq_data *d = irq_get_irq_data(irq);
struct irq_chip *c = irq_data_get_irq_chip(d);
c->irq_mask(d);
local_irq_disable();
/* Clear the IRQ from the ENABLE_SET */
gic_clear_irq_pending(irq);
local_irq_enable();
}
static void clear_pending_spi(unsigned int irq)
{
struct irq_data *d = irq_get_irq_data(irq);
struct irq_chip *c = irq_data_get_irq_chip(d);
c->irq_mask(d);
local_irq_disable();
gic_clear_irq_pending(irq);
local_irq_enable();
}
/* Called from the FIQ bark handler */
void msm_7k_bark_fin(void)
{
fiq_counter++;
// local_irq_disable();
//clear_pending_spi(MSM8625_INT_A9_M2A_2);
gic_clear_irq_pending(MSM8625_INT_A9_M2A_2);
//gic_clear_spi_pending(MSM8625_INT_A9_M2A_2);
//local_irq_enable();
flush_cache_all();
outer_flush_all();
return;
}
/* Called from the FIQ asm handler */
void msm7k_fiq_handler(void)
{
struct irq_data *d;
struct irq_chip *c;
pr_info("Fiq is received %s\n", __func__);
fiq_counter++;
d = irq_get_irq_data(MSM8625_INT_A9_M2A_2);
c = irq_data_get_irq_chip(d);
c->irq_mask(d);
local_irq_disable();
/* Clear the IRQ from the ENABLE_SET */
gic_clear_irq_pending(MSM8625_INT_A9_M2A_2);
local_irq_enable();
flush_cache_all();
outer_flush_all();
return;
}
/* Called from the FIQ asm handler */
void msm7k_fiq_handler(void)
{
struct irq_data *d;
struct irq_chip *c;
struct pt_regs ctx_regs;
pr_info("Fiq is received %s\n", __func__);
fiq_counter++;
d = irq_get_irq_data(MSM8625_INT_A9_M2A_2);
c = irq_data_get_irq_chip(d);
c->irq_mask(d);
local_irq_disable();
/* Clear the IRQ from the ENABLE_SET */
gic_clear_irq_pending(MSM8625_INT_A9_M2A_2);
local_irq_enable();
ctx_regs.ARM_pc = msm_dump_cpu_ctx.fiq_r14;
ctx_regs.ARM_lr = msm_dump_cpu_ctx.svc_r14;
ctx_regs.ARM_sp = msm_dump_cpu_ctx.svc_r13;
ctx_regs.ARM_fp = msm_dump_cpu_ctx.usr_r11;
#ifdef CONFIG_SEC_DEBUG
do {
extern void sec_save_final_context(void);
sec_save_final_context();
} while (0);
#endif
unwind_backtrace(&ctx_regs, current);
#ifdef CONFIG_SMP
smp_send_all_cpu_backtrace();
#endif
flush_cache_all();
outer_flush_all();
return;
}
