int board_init(void) { /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_NAND_ATMEL sama5d3xek_nand_hw_init(); #endif #ifdef CONFIG_MTD_NOR_FLASH sama5d3xek_nor_hw_init(); #endif #ifdef CONFIG_CMD_USB sama5d3xek_usb_hw_init(); #endif #ifdef CONFIG_USB_GADGET_ATMEL_USBA at91_udp_hw_init(); #endif #ifdef CONFIG_GENERIC_ATMEL_MCI sama5d3xek_mci_hw_init(); #endif #ifdef CONFIG_ATMEL_SPI at91_spi0_hw_init(1 << 0); #endif #ifdef CONFIG_MACB if (has_emac()) at91_macb_hw_init(); if (has_gmac()) at91_gmac_hw_init(); #endif #ifdef CONFIG_LCD if (has_lcdc()) sama5d3xek_lcd_hw_init(); #endif return 0; }
static void at91sam9x5ek_lcd_hw_init(void) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; if (has_lcdc()) { at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDPWM */ at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDVSYNC */ at91_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDHSYNC */ at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDISP */ at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */ at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDPCK */ at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */ at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */ at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */ at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */ at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */ at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */ at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */ at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */ at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */ at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */ at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */ at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */ at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */ at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */ at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */ at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */ at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */ at91_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */ at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */ at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */ at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */ at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */ at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */ at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */ writel(1 << ATMEL_ID_LCDC, &pmc->pcer); } }
static void at91sam9x5ek_lcd_hw_init(void) { if (has_lcdc()) { at91_pio3_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDPWM */ at91_pio3_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDVSYNC */ at91_pio3_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDHSYNC */ at91_pio3_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDISP */ at91_pio3_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */ at91_pio3_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDPCK */ at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */ at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */ at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */ at91_pio3_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */ at91_pio3_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */ at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */ at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */ at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */ at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */ at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */ at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */ at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */ at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */ at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */ at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */ at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */ at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */ at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */ at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */ at91_pio3_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */ at91_pio3_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */ at91_pio3_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */ at91_pio3_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */ at91_pio3_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */ at91_periph_clk_enable(ATMEL_ID_LCDC); } }
void lcd_disable(void) { if (has_lcdc()) at91_pio3_set_a_periph(AT91_PIO_PORTC, 29, 0); /* power down */ }
void lcd_enable(void) { if (has_lcdc()) at91_pio3_set_a_periph(AT91_PIO_PORTC, 29, 1); /* power up */ }
void lcd_ctrl_init(void *lcdbase) { unsigned long value; struct lcd_dma_desc *desc; struct atmel_hlcd_regs *regs; if (!has_lcdc()) return; /* No lcdc */ regs = (struct atmel_hlcd_regs *)panel_info.mmio; /* Disable DISP signal */ lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_DISPDIS); while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_DISPSTS)) udelay(1); /* Disable synchronization */ lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_SYNCDIS); while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_LCDSTS)) udelay(1); /* Disable pixel clock */ lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_CLKDIS); while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_CLKSTS)) udelay(1); /* Disable PWM */ lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_PWMDIS); while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS)) udelay(1); /* Set pixel clock */ value = get_lcdc_clk_rate(0) / panel_info.vl_clk; if (get_lcdc_clk_rate(0) % panel_info.vl_clk) value++; if (value < 1) { /* Using system clock as pixel clock */ lcdc_writel(®s->lcdc_lcdcfg0, LCDC_LCDCFG0_CLKDIV(0) | LCDC_LCDCFG0_CGDISHCR | LCDC_LCDCFG0_CGDISHEO | LCDC_LCDCFG0_CGDISOVR1 | LCDC_LCDCFG0_CGDISBASE | panel_info.vl_clk_pol | LCDC_LCDCFG0_CLKSEL); } else { lcdc_writel(®s->lcdc_lcdcfg0, LCDC_LCDCFG0_CLKDIV(value - 2) | LCDC_LCDCFG0_CGDISHCR | LCDC_LCDCFG0_CGDISHEO | LCDC_LCDCFG0_CGDISOVR1 | LCDC_LCDCFG0_CGDISBASE | panel_info.vl_clk_pol); } /* Initialize control register 5 */ value = 0; value |= panel_info.vl_sync; #ifndef LCD_OUTPUT_BPP /* Output is 24bpp */ value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP; #else switch (LCD_OUTPUT_BPP) { case 12: value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP; break; case 16: value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP; break; case 18: value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP; break; case 24: value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP; break; default: BUG(); break; } #endif value |= LCDC_LCDCFG5_GUARDTIME(ATMEL_LCDC_GUARD_TIME); value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS); lcdc_writel(®s->lcdc_lcdcfg5, value); /* Vertical & Horizontal Timing */ value = LCDC_LCDCFG1_VSPW(panel_info.vl_vsync_len - 1); value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1); lcdc_writel(®s->lcdc_lcdcfg1, value); value = LCDC_LCDCFG2_VBPW(panel_info.vl_lower_margin); value |= LCDC_LCDCFG2_VFPW(panel_info.vl_upper_margin - 1); lcdc_writel(®s->lcdc_lcdcfg2, value); value = LCDC_LCDCFG3_HBPW(panel_info.vl_right_margin - 1); value |= LCDC_LCDCFG3_HFPW(panel_info.vl_left_margin - 1); lcdc_writel(®s->lcdc_lcdcfg3, value); /* Display size */ value = LCDC_LCDCFG4_RPF(panel_info.vl_row - 1); value |= LCDC_LCDCFG4_PPL(panel_info.vl_col - 1); lcdc_writel(®s->lcdc_lcdcfg4, value); lcdc_writel(®s->lcdc_basecfg0, LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO); switch (NBITS(panel_info.vl_bpix)) { case 16: lcdc_writel(®s->lcdc_basecfg1, LCDC_BASECFG1_RGBMODE_16BPP_RGB_565); break; default: BUG(); break; } lcdc_writel(®s->lcdc_basecfg2, LCDC_BASECFG2_XSTRIDE(0)); lcdc_writel(®s->lcdc_basecfg3, 0); lcdc_writel(®s->lcdc_basecfg4, LCDC_BASECFG4_DMA); /* Disable all interrupts */ lcdc_writel(®s->lcdc_lcdidr, ~0UL); lcdc_writel(®s->lcdc_baseidr, ~0UL); /* Setup the DMA descriptor, this descriptor will loop to itself */ desc = (struct lcd_dma_desc *)(lcdbase - 16); desc->address = (u32)lcdbase; /* Disable DMA transfer interrupt & descriptor loaded interrupt. */ desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH; desc->next = (u32)desc; lcdc_writel(®s->lcdc_baseaddr, desc->address); lcdc_writel(®s->lcdc_basectrl, desc->control); lcdc_writel(®s->lcdc_basenext, desc->next); lcdc_writel(®s->lcdc_basecher, LCDC_BASECHER_CHEN | LCDC_BASECHER_UPDATEEN); /* Enable LCD */ value = lcdc_readl(®s->lcdc_lcden); lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_CLKEN); while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_CLKSTS)) udelay(1); value = lcdc_readl(®s->lcdc_lcden); lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_SYNCEN); while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_LCDSTS)) udelay(1); value = lcdc_readl(®s->lcdc_lcden); lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_DISPEN); while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_DISPSTS)) udelay(1); value = lcdc_readl(®s->lcdc_lcden); lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_PWMEN); while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS)) udelay(1); }
void lcd_ctrl_init(void *lcdbase) { unsigned long value; struct lcd_dma_desc *desc; struct atmel_hlcd_regs *regs; int ret; if (!has_lcdc()) return; /* No lcdc */ regs = (struct atmel_hlcd_regs *)panel_info.mmio; /* Disable DISP signal */ writel(LCDC_LCDDIS_DISPDIS, ®s->lcdc_lcddis); ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_DISPSTS, false, 1000, false); if (ret) printf("%s: %d: Timeout!\n", __func__, __LINE__); /* Disable synchronization */ writel(LCDC_LCDDIS_SYNCDIS, ®s->lcdc_lcddis); ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_LCDSTS, false, 1000, false); if (ret) printf("%s: %d: Timeout!\n", __func__, __LINE__); /* Disable pixel clock */ writel(LCDC_LCDDIS_CLKDIS, ®s->lcdc_lcddis); ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_CLKSTS, false, 1000, false); if (ret) printf("%s: %d: Timeout!\n", __func__, __LINE__); /* Disable PWM */ writel(LCDC_LCDDIS_PWMDIS, ®s->lcdc_lcddis); ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_PWMSTS, false, 1000, false); if (ret) printf("%s: %d: Timeout!\n", __func__, __LINE__); /* Set pixel clock */ value = get_lcdc_clk_rate(0) / panel_info.vl_clk; if (get_lcdc_clk_rate(0) % panel_info.vl_clk) value++; if (value < 1) { /* Using system clock as pixel clock */ writel(LCDC_LCDCFG0_CLKDIV(0) | LCDC_LCDCFG0_CGDISHCR | LCDC_LCDCFG0_CGDISHEO | LCDC_LCDCFG0_CGDISOVR1 | LCDC_LCDCFG0_CGDISBASE | panel_info.vl_clk_pol | LCDC_LCDCFG0_CLKSEL, ®s->lcdc_lcdcfg0); } else { writel(LCDC_LCDCFG0_CLKDIV(value - 2) | LCDC_LCDCFG0_CGDISHCR | LCDC_LCDCFG0_CGDISHEO | LCDC_LCDCFG0_CGDISOVR1 | LCDC_LCDCFG0_CGDISBASE | panel_info.vl_clk_pol, ®s->lcdc_lcdcfg0); } /* Initialize control register 5 */ value = 0; value |= panel_info.vl_sync; #ifndef LCD_OUTPUT_BPP /* Output is 24bpp */ value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP; #else switch (LCD_OUTPUT_BPP) { case 12: value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP; break; case 16: value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP; break; case 18: value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP; break; case 24: value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP; break; default: BUG(); break; } #endif value |= LCDC_LCDCFG5_GUARDTIME(ATMEL_LCDC_GUARD_TIME); value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS); writel(value, ®s->lcdc_lcdcfg5); /* Vertical & Horizontal Timing */ value = LCDC_LCDCFG1_VSPW(panel_info.vl_vsync_len - 1); value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1); writel(value, ®s->lcdc_lcdcfg1); value = LCDC_LCDCFG2_VBPW(panel_info.vl_upper_margin); value |= LCDC_LCDCFG2_VFPW(panel_info.vl_lower_margin - 1); writel(value, ®s->lcdc_lcdcfg2); value = LCDC_LCDCFG3_HBPW(panel_info.vl_left_margin - 1); value |= LCDC_LCDCFG3_HFPW(panel_info.vl_right_margin - 1); writel(value, ®s->lcdc_lcdcfg3); /* Display size */ value = LCDC_LCDCFG4_RPF(panel_info.vl_row - 1); value |= LCDC_LCDCFG4_PPL(panel_info.vl_col - 1); writel(value, ®s->lcdc_lcdcfg4); writel(LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO, ®s->lcdc_basecfg0); switch (NBITS(panel_info.vl_bpix)) { case 16: writel(LCDC_BASECFG1_RGBMODE_16BPP_RGB_565, ®s->lcdc_basecfg1); break; case 32: writel(LCDC_BASECFG1_RGBMODE_24BPP_RGB_888, ®s->lcdc_basecfg1); break; default: BUG(); break; } writel(LCDC_BASECFG2_XSTRIDE(0), ®s->lcdc_basecfg2); writel(0, ®s->lcdc_basecfg3); writel(LCDC_BASECFG4_DMA, ®s->lcdc_basecfg4); /* Disable all interrupts */ writel(~0UL, ®s->lcdc_lcdidr); writel(~0UL, ®s->lcdc_baseidr); /* Setup the DMA descriptor, this descriptor will loop to itself */ desc = (struct lcd_dma_desc *)(lcdbase - 16); desc->address = (u32)lcdbase; /* Disable DMA transfer interrupt & descriptor loaded interrupt. */ desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH; desc->next = (u32)desc; /* Flush the DMA descriptor if we enabled dcache */ flush_dcache_range((u32)desc, (u32)desc + sizeof(*desc)); writel(desc->address, ®s->lcdc_baseaddr); writel(desc->control, ®s->lcdc_basectrl); writel(desc->next, ®s->lcdc_basenext); writel(LCDC_BASECHER_CHEN | LCDC_BASECHER_UPDATEEN, ®s->lcdc_basecher); /* Enable LCD */ value = readl(®s->lcdc_lcden); writel(value | LCDC_LCDEN_CLKEN, ®s->lcdc_lcden); ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_CLKSTS, true, 1000, false); if (ret) printf("%s: %d: Timeout!\n", __func__, __LINE__); value = readl(®s->lcdc_lcden); writel(value | LCDC_LCDEN_SYNCEN, ®s->lcdc_lcden); ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_LCDSTS, true, 1000, false); if (ret) printf("%s: %d: Timeout!\n", __func__, __LINE__); value = readl(®s->lcdc_lcden); writel(value | LCDC_LCDEN_DISPEN, ®s->lcdc_lcden); ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_DISPSTS, true, 1000, false); if (ret) printf("%s: %d: Timeout!\n", __func__, __LINE__); value = readl(®s->lcdc_lcden); writel(value | LCDC_LCDEN_PWMEN, ®s->lcdc_lcden); ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_PWMSTS, true, 1000, false); if (ret) printf("%s: %d: Timeout!\n", __func__, __LINE__); /* Enable flushing if we enabled dcache */ lcd_set_flush_dcache(1); }