static void test_cmd53_read_write_multiple_bytes(sdmmc_card_t* card, size_t n_bytes)
{
printf("Write multiple bytes using CMD53\n");
const size_t scratch_area_reg = SLCHOST_CONF_W0 - DR_REG_SLCHOST_BASE;
uint8_t* src = heap_caps_malloc(512, MALLOC_CAP_DMA);
uint32_t* src_32 = (uint32_t*) src;
for (size_t i = 0; i < (n_bytes + 3) / 4; ++i) {
src_32[i] = rand();
}
TEST_ESP_OK(sdmmc_io_write_bytes(card, 1, scratch_area_reg, src, n_bytes));
ESP_LOG_BUFFER_HEX(TAG, src, n_bytes);
printf("Read back using CMD52\n");
uint8_t* dst = heap_caps_malloc(512, MALLOC_CAP_DMA);
for (size_t i = 0; i < n_bytes; ++i) {
TEST_ESP_OK(sdmmc_io_read_byte(card, 1, scratch_area_reg + i, &dst[i]));
}
ESP_LOG_BUFFER_HEX(TAG, dst, n_bytes);
TEST_ASSERT_EQUAL_UINT8_ARRAY(src, dst, n_bytes);
printf("Read back using CMD53\n");
TEST_ESP_OK(sdmmc_io_read_bytes(card, 1, scratch_area_reg, dst, n_bytes));
ESP_LOG_BUFFER_HEX(TAG, dst, n_bytes);
TEST_ASSERT_EQUAL_UINT8_ARRAY(src, dst, n_bytes);
free(src);
free(dst);
}
static void test_psram_content()
{
const int test_size = 2048;
uint32_t *test_area = heap_caps_malloc(test_size, MALLOC_CAP_SPIRAM);
size_t p;
size_t s=test_size;
int errct=0;
int initial_err=-1;
for (p=0; p<(s/sizeof(int)); p+=4) {
test_area[p]=p^0xAAAAAAAA;
}
for (p=0; p<(s/sizeof(int)); p+=4) {
if (test_area[p]!=(p^0xAAAAAAAA)) {
errct++;
if (errct==1) initial_err=p*4;
}
}
if (errct) {
ESP_LOGE(TAG, "SPI SRAM memory test fail. %d/%d writes failed, first @ %p\n", errct, s/32, initial_err+test_area);
TEST_FAIL();
} else {
ESP_LOGI(TAG, "SPI SRAM memory test OK");
}
free(test_area);
}
esp_err_t adc_init(adc_config_t *config)
{
ADC_CHECK(config, "config error", ESP_ERR_INVALID_ARG);
ADC_CHECK(NULL == adc_handle, "adc has been initialized", ESP_FAIL);
uint8_t vdd33_const;
esp_phy_init_data_t *phy_init_data;
phy_init_data = (esp_phy_init_data_t *)esp_phy_get_init_data();
vdd33_const = phy_init_data->params[107];
ADC_CHECK((config->mode == ADC_READ_TOUT_MODE) ? (vdd33_const < 255) : true, "To read the external voltage on TOUT(ADC) pin, vdd33_const need less than 255", ESP_FAIL);
ADC_CHECK((config->mode == ADC_READ_VDD_MODE) ? (vdd33_const == 255) : true, "When adc measuring system voltage, vdd33_const must be set to 255,", ESP_FAIL);
ADC_CHECK(config->mode <= ADC_READ_MAX_MODE, "adc mode err", ESP_FAIL);
adc_handle = heap_caps_malloc(sizeof(adc_handle_t), MALLOC_CAP_8BIT);
ADC_CHECK(adc_handle, "adc handle malloc error", ESP_ERR_NO_MEM);
memcpy(&adc_handle->config, config, sizeof(adc_config_t));
adc_handle->adc_mux = xSemaphoreCreateMutex();
if (NULL == adc_handle->adc_mux) {
adc_deinit();
ADC_CHECK(false, "Semaphore create fail", ESP_ERR_NO_MEM);
}
return ESP_OK;
}
esp_err_t sdmmc_init_mmc_read_ext_csd(sdmmc_card_t* card)
{
int card_type;
esp_err_t err = ESP_OK;
uint8_t* ext_csd = heap_caps_malloc(EXT_CSD_MMC_SIZE, MALLOC_CAP_DMA);
if (!ext_csd) {
ESP_LOGE(TAG, "%s: could not allocate ext_csd", __func__);
return ESP_ERR_NO_MEM;
}
uint32_t sectors = 0;
ESP_LOGD(TAG, "MMC version: %d", card->csd.mmc_ver);
if (card->csd.mmc_ver < MMC_CSD_MMCVER_4_0) {
err = ESP_ERR_NOT_SUPPORTED;
goto out;
}
/* read EXT_CSD */
err = sdmmc_mmc_send_ext_csd_data(card, ext_csd, EXT_CSD_MMC_SIZE);
if (err != ESP_OK) {
ESP_LOGE(TAG, "%s: send_ext_csd_data error 0x%x", __func__, err);
goto out;
}
card_type = ext_csd[EXT_CSD_CARD_TYPE];
card->is_ddr = 0;
if (card_type & EXT_CSD_CARD_TYPE_F_52M_1_8V) {
card->max_freq_khz = SDMMC_FREQ_52M;
if ((card->host.flags & SDMMC_HOST_FLAG_DDR) &&
card->host.max_freq_khz >= SDMMC_FREQ_26M &&
card->host.get_bus_width(card->host.slot) == 4) {
ESP_LOGD(TAG, "card and host support DDR mode");
card->is_ddr = 1;
}
} else if (card_type & EXT_CSD_CARD_TYPE_F_52M) {
card->max_freq_khz = SDMMC_FREQ_52M;
} else if (card_type & EXT_CSD_CARD_TYPE_F_26M) {
card->max_freq_khz = SDMMC_FREQ_26M;
} else {
ESP_LOGW(TAG, "%s: unknown CARD_TYPE 0x%x", __func__, card_type);
}
/* For MMC cards, use speed value from EXT_CSD */
card->csd.tr_speed = card->max_freq_khz * 1000;
ESP_LOGD(TAG, "MMC card type %d, max_freq_khz=%d, is_ddr=%d", card_type, card->max_freq_khz, card->is_ddr);
card->max_freq_khz = MIN(card->max_freq_khz, card->host.max_freq_khz);
if (card->host.flags & SDMMC_HOST_FLAG_8BIT) {
card->ext_csd.power_class = ext_csd[(card->max_freq_khz > SDMMC_FREQ_26M) ?
EXT_CSD_PWR_CL_52_360 : EXT_CSD_PWR_CL_26_360] >> 4;
card->log_bus_width = 3;
} else if (card->host.flags & SDMMC_HOST_FLAG_4BIT) {
wifi_static_queue_t* wifi_create_queue( int queue_len, int item_size)
{
wifi_static_queue_t *queue = NULL;
queue = (wifi_static_queue_t*)heap_caps_malloc(sizeof(wifi_static_queue_t), MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT);
if (!queue) {
return NULL;
}
#if 0 /* TODO: CONFIG_SPIRAM_USE_MALLOC */
queue->storage = heap_caps_calloc(1, sizeof(StaticQueue_t) + (queue_len*item_size), MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT);
if (!queue->storage) {
goto _error;
}
queue->handle = xQueueCreateStatic( queue_len, item_size, ((uint8_t*)(queue->storage)) + sizeof(StaticQueue_t), (StaticQueue_t*)(queue->storage));
if (!queue->handle) {
goto _error;
}
return queue;
_error:
if (queue) {
if (queue->storage) {
free(queue->storage);
}
free(queue);
}
return NULL;
#else
queue->handle = xQueueCreate( queue_len, item_size);
return queue;
#endif
}
esp_err_t spi_bus_initialize(spi_host_device_t host, const spi_bus_config_t *bus_config, int dma_chan)
{
bool native, spi_chan_claimed, dma_chan_claimed;
/* ToDo: remove this when we have flash operations cooperating with this */
SPI_CHECK(host!=SPI_HOST, "SPI1 is not supported", ESP_ERR_NOT_SUPPORTED);
SPI_CHECK(host>=SPI_HOST && host<=VSPI_HOST, "invalid host", ESP_ERR_INVALID_ARG);
SPI_CHECK( dma_chan >= 0 && dma_chan <= 2, "invalid dma channel", ESP_ERR_INVALID_ARG );
spi_chan_claimed=spicommon_periph_claim(host);
SPI_CHECK(spi_chan_claimed, "host already in use", ESP_ERR_INVALID_STATE);
if ( dma_chan != 0 ) {
dma_chan_claimed=spicommon_dma_chan_claim(dma_chan);
if ( !dma_chan_claimed ) {
spicommon_periph_free( host );
SPI_CHECK(dma_chan_claimed, "dma channel already in use", ESP_ERR_INVALID_STATE);
}
}
spihost[host]=malloc(sizeof(spi_host_t));
if (spihost[host]==NULL) goto nomem;
memset(spihost[host], 0, sizeof(spi_host_t));
#ifdef CONFIG_PM_ENABLE
esp_err_t err = esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, "spi_master",
&spihost[host]->pm_lock);
if (err != ESP_OK) {
goto nomem;
}
#endif //CONFIG_PM_ENABLE
spicommon_bus_initialize_io(host, bus_config, dma_chan, SPICOMMON_BUSFLAG_MASTER|SPICOMMON_BUSFLAG_QUAD, &native);
spihost[host]->no_gpio_matrix=native;
spihost[host]->dma_chan=dma_chan;
if (dma_chan == 0) {
spihost[host]->max_transfer_sz = 32;
} else {
//See how many dma descriptors we need and allocate them
int dma_desc_ct=(bus_config->max_transfer_sz+SPI_MAX_DMA_LEN-1)/SPI_MAX_DMA_LEN;
if (dma_desc_ct==0) dma_desc_ct=1; //default to 4k when max is not given
spihost[host]->max_transfer_sz = dma_desc_ct*SPI_MAX_DMA_LEN;
spihost[host]->dmadesc_tx=heap_caps_malloc(sizeof(lldesc_t)*dma_desc_ct, MALLOC_CAP_DMA);
spihost[host]->dmadesc_rx=heap_caps_malloc(sizeof(lldesc_t)*dma_desc_ct, MALLOC_CAP_DMA);
if (!spihost[host]->dmadesc_tx || !spihost[host]->dmadesc_rx) goto nomem;
}
esp_intr_alloc(spicommon_irqsource_for_host(host), ESP_INTR_FLAG_INTRDISABLED, spi_intr, (void*)spihost[host], &spihost[host]->intr);
spihost[host]->hw=spicommon_hw_for_host(host);
spihost[host]->cur_cs = NO_CS;
spihost[host]->prev_cs = NO_CS;
//Reset DMA
spihost[host]->hw->dma_conf.val|=SPI_OUT_RST|SPI_IN_RST|SPI_AHBM_RST|SPI_AHBM_FIFO_RST;
spihost[host]->hw->dma_out_link.start=0;
spihost[host]->hw->dma_in_link.start=0;
spihost[host]->hw->dma_conf.val&=~(SPI_OUT_RST|SPI_IN_RST|SPI_AHBM_RST|SPI_AHBM_FIFO_RST);
//Reset timing
spihost[host]->hw->ctrl2.val=0;
//Disable unneeded ints
spihost[host]->hw->slave.rd_buf_done=0;
spihost[host]->hw->slave.wr_buf_done=0;
spihost[host]->hw->slave.rd_sta_done=0;
spihost[host]->hw->slave.wr_sta_done=0;
spihost[host]->hw->slave.rd_buf_inten=0;
spihost[host]->hw->slave.wr_buf_inten=0;
spihost[host]->hw->slave.rd_sta_inten=0;
spihost[host]->hw->slave.wr_sta_inten=0;
//Force a transaction done interrupt. This interrupt won't fire yet because we initialized the SPI interrupt as
//disabled. This way, we can just enable the SPI interrupt and the interrupt handler will kick in, handling
//any transactions that are queued.
spihost[host]->hw->slave.trans_inten=1;
spihost[host]->hw->slave.trans_done=1;
return ESP_OK;
nomem:
if (spihost[host]) {
free(spihost[host]->dmadesc_tx);
free(spihost[host]->dmadesc_rx);
#ifdef CONFIG_PM_ENABLE
if (spihost[host]->pm_lock) {
esp_pm_lock_delete(spihost[host]->pm_lock);
}
#endif
}
free(spihost[host]);
spicommon_periph_free(host);
spicommon_dma_chan_free(dma_chan);
return ESP_ERR_NO_MEM;
}
static void * IRAM_ATTR malloc_internal_wrapper(size_t size)
{
return heap_caps_malloc(size, MALLOC_CAP_DEFAULT|MALLOC_CAP_INTERNAL);
}
{
char *m1, *m2[10];
int x;
size_t free8start, free32start, free8, free32;
/* It's important we printf() something before we take the empty heap sizes,
as the first printf() in a task allocates heap resources... */
printf("Testing capabilities allocator...\n");
free8start = heap_caps_get_free_size(MALLOC_CAP_8BIT);
free32start = heap_caps_get_free_size(MALLOC_CAP_32BIT);
printf("Free 8bit-capable memory (start): %dK, 32-bit capable memory %dK\n", free8start, free32start);
TEST_ASSERT(free32start>free8start);
printf("Allocating 10K of 8-bit capable RAM\n");
m1= heap_caps_malloc(10*1024, MALLOC_CAP_8BIT);
printf("--> %p\n", m1);
free8 = heap_caps_get_free_size(MALLOC_CAP_8BIT);
free32 = heap_caps_get_free_size(MALLOC_CAP_32BIT);
printf("Free 8bit-capable memory (both reduced): %dK, 32-bit capable memory %dK\n", free8, free32);
//Both should have gone down by 10K; 8bit capable ram is also 32-bit capable
TEST_ASSERT(free8<(free8start-10*1024));
TEST_ASSERT(free32<(free32start-10*1024));
//Assume we got DRAM back
TEST_ASSERT((((int)m1)&0xFF000000)==0x3F000000);
free(m1);
printf("Freeing; allocating 10K of 32K-capable RAM\n");
m1 = heap_caps_malloc(10*1024, MALLOC_CAP_32BIT);
printf("--> %p\n", m1);
free8 = heap_caps_get_free_size(MALLOC_CAP_8BIT);
