static void hotplug_event_clear(PCIDevice *dev)
{
hotplug_event_update_event_status(dev);
if (!msix_enabled(dev) && !msi_enabled(dev) && !dev->exp.hpev_notified) {
pci_irq_deassert(dev);
}
}
void pcie_cap_slot_reset(PCIDevice *dev)
{
uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
PCIE_DEV_PRINTF(dev, "reset\n");
pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
PCI_EXP_SLTCTL_EIC |
PCI_EXP_SLTCTL_PIC |
PCI_EXP_SLTCTL_AIC |
PCI_EXP_SLTCTL_HPIE |
PCI_EXP_SLTCTL_CCIE |
PCI_EXP_SLTCTL_PDCE |
PCI_EXP_SLTCTL_ABPE);
pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL,
PCI_EXP_SLTCTL_PIC_OFF |
PCI_EXP_SLTCTL_AIC_OFF);
pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA,
PCI_EXP_SLTSTA_EIS |/* on reset,
the lock is released */
PCI_EXP_SLTSTA_CC |
PCI_EXP_SLTSTA_PDC |
PCI_EXP_SLTSTA_ABP);
hotplug_event_update_event_status(dev);
}
static void hotplug_event_clear(PCIDevice *dev)
{
hotplug_event_update_event_status(dev);
if (!msix_enabled(dev) && !msi_enabled(dev) && !dev->exp.hpev_notified) {
qemu_set_irq(dev->irq[dev->exp.hpev_intx], 0);
}
}
void pcie_cap_slot_reset(PCIDevice *dev)
{
uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
uint8_t port_type = pcie_cap_get_type(dev);
assert(port_type == PCI_EXP_TYPE_DOWNSTREAM ||
port_type == PCI_EXP_TYPE_ROOT_PORT);
PCIE_DEV_PRINTF(dev, "reset\n");
pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
PCI_EXP_SLTCTL_EIC |
PCI_EXP_SLTCTL_PIC |
PCI_EXP_SLTCTL_AIC |
PCI_EXP_SLTCTL_HPIE |
PCI_EXP_SLTCTL_CCIE |
PCI_EXP_SLTCTL_PDCE |
PCI_EXP_SLTCTL_ABPE);
pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL,
PCI_EXP_SLTCTL_AIC_OFF);
if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) {
/* Downstream ports enforce device number 0. */
bool populated = pci_bridge_get_sec_bus(PCI_BRIDGE(dev))->devices[0];
uint16_t pic;
if (populated) {
pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
PCI_EXP_SLTCTL_PCC);
} else {
pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL,
PCI_EXP_SLTCTL_PCC);
}
pic = populated ? PCI_EXP_SLTCTL_PIC_ON : PCI_EXP_SLTCTL_PIC_OFF;
pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, pic);
}
pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA,
PCI_EXP_SLTSTA_EIS |/* on reset,
the lock is released */
PCI_EXP_SLTSTA_CC |
PCI_EXP_SLTSTA_PDC |
PCI_EXP_SLTSTA_ABP);
hotplug_event_update_event_status(dev);
}
static void hotplug_event_notify(PCIDevice *dev)
{
bool prev = dev->exp.hpev_notified;
hotplug_event_update_event_status(dev);
if (prev == dev->exp.hpev_notified) {
return;
}
/* Note: the logic above does not take into account whether interrupts
* are masked. The result is that interrupt will be sent when it is
* subsequently unmasked. This appears to be legal: Section 6.7.3.4:
* The Port may optionally send an MSI when there are hot-plug events that
* occur while interrupt generation is disabled, and interrupt generation is
* subsequently enabled. */
if (msix_enabled(dev)) {
msix_notify(dev, pcie_cap_flags_get_vector(dev));
} else if (msi_enabled(dev)) {
msi_notify(dev, pcie_cap_flags_get_vector(dev));
} else {
pci_set_irq(dev, dev->exp.hpev_notified);
}
}
int pcie_cap_slot_post_load(void *opaque, int version_id)
{
PCIDevice *dev = opaque;
hotplug_event_update_event_status(dev);
return 0;
}
