static inline void PPRZ_I2C_SEND_START(struct i2c_periph *periph)
{
uint32_t i2c = (uint32_t) periph->reg_addr;
// Reset the buffer pointer to the first byte
periph->idx_buf = 0;
#ifdef I2C_DEBUG_LED
LED_SHOW_ACTIVE_BITS(regs);
LED2_ON();
LED1_ON();
LED1_OFF();
LED1_ON();
LED1_OFF();
LED1_ON();
LED1_OFF();
LED2_OFF();
#endif
// Enable Error IRQ, Event IRQ but disable Buffer IRQ
i2c_enable_interrupt(i2c, I2C_CR2_ITERREN);
i2c_enable_interrupt(i2c, I2C_CR2_ITEVTEN);
i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
// Issue a new start
i2c_nack_current(i2c);
i2c_disable_ack(i2c);
i2c_clear_stop(i2c);
i2c_peripheral_enable(i2c);
i2c_send_start(i2c);
periph->status = I2CStartRequested;
}
// Doc ID 13902 Rev 11 p 714/1072
// Transfer Sequence Diagram for Master Receiver for N=1
static inline enum STMI2CSubTransactionStatus stmi2c_read1(uint32_t i2c, struct i2c_periph *periph, struct i2c_transaction *trans)
{
uint16_t SR1 = I2C_SR1(i2c);
// Start Condition Was Just Generated
if (BIT_X_IS_SET_IN_REG( I2C_SR1_SB, SR1 ) )
{
i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
i2c_send_data(i2c, trans->slave_addr | 0x01);
// Document the current Status
periph->status = I2CAddrRdSent;
}
// Address Was Sent
else if (BIT_X_IS_SET_IN_REG(I2C_SR1_ADDR, SR1) )
{
// First Clear the ACK bit: after the next byte we do not want new bytes
i2c_nack_current(i2c);
i2c_disable_ack(i2c);
// --- next to steps MUST be executed together to avoid missing the stop
__I2C_REG_CRITICAL_ZONE_START;
// Only after setting ACK, read SR2 to clear the ADDR (next byte will start arriving)
uint16_t SR2 __attribute__ ((unused)) = I2C_SR2(i2c);
// Schedule a Stop
PPRZ_I2C_SEND_STOP(i2c);
__I2C_REG_CRITICAL_ZONE_STOP;
// --- end of critical zone -----------
// Enable the RXNE: it will trigger as soon as the 1 byte is received to get the result
i2c_enable_interrupt(i2c, I2C_CR2_ITBUFEN);
// Document the current Status
periph->status = I2CReadingLastByte;
}
// As soon as there is 1 byte ready to read, we have our byte
else if (BIT_X_IS_SET_IN_REG(I2C_SR1_RxNE, SR1) )
{
i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
trans->buf[0] = I2C_DR(i2c);
// We got all the results (stop condition might still be in progress but this is the last interrupt)
trans->status = I2CTransSuccess;
// Document the current Status:
// -the stop was actually already requested in the previous step
periph->status = I2CStopRequested;
return STMI2C_SubTra_Ready_StopRequested;
}
else // Event Logic Error
{
return STMI2C_SubTra_Error;
}
return STMI2C_SubTra_Busy;
}
int i2c_master_recv_data(unsigned int addr,
unsigned char *data, unsigned int len)
{
unsigned int i = 0;
int ret = 0;
ret = i2c_set_master(); // get iic bus, as bus master;
if (ret) {
putstring("\nget i2c bus error\n");
return ret; // error while getting bus
}
i2c_enable_irq();
i2c_message_start(addr, 1);
while (1) {
i++;
if (i == len) { // last byte
i2c_disable_ack();
break;
}
*data++ = IICDS;
IICCON &= ~(1 << 4); // resume trasmit
// TODO dealy ??
for (ret = 0; ret < 30; ret++) ; // setup time
}
/* last byte */
*data++ = IICDS;
IICCON &= ~(1 << 4); // resume trasmit
// TODO dealy ??
for (ret = 0; ret < 30; ret++) ; // setup time
return len;
}
/**
* @brief Reads multiple 8-bit registers from an I2C slave
* @param[in] slaveId The slave device ID
* @param[in] startRegisterAddress The first register address
* @param[in] registerCount The number of registers to read; Must be greater than or equal to two.
* @param[out] buffer The buffer to write into
* @return 0 is successful, 1 if not
*/
static int i2c_read_registers_internal(register uint8_t slaveId, register uint8_t startRegisterAddress, register uint8_t registerCount, uint8_t *const buffer){
if(registerCount < 2)
return -1;
/* loop while the bus is still busy */
i2c_wait_while_busy();
/* send I2C start signal and set write direction, also enables ACK */
i2c_send_start();
/* send the slave address and wait for the I2C bus operation to complete */
i2c_send_byte(I2C_WRITE_ADDRESS(slaveId));
/* send the register address */
i2c_send_byte(startRegisterAddress);
/* signal a repeated start condition */
i2c_send_repeated_start();
/* send the read address */
i2c_send_byte(I2C_READ_ADDRESS(slaveId));
/* switch to receive mode and assume more than one register */
i2c_enter_receive_mode_with_ack();
/* read a dummy byte to drive the clock */
i2c_read_dummy_byte();
/* for all remaining bytes, read */
--registerCount;
uint8_t index = 0;
while (--registerCount > 0)
{
/* fetch and store value */
register uint8_t value = I2C0->D;
buffer[index++] = value;
/* wait for completion */
i2c_wait();
}
/* disable ACK and read second-to-last byte */
i2c_disable_ack();
/* fetch and store value */
buffer[index++] = I2C0->D;
/* wait for completion */
i2c_wait();
/* stop signal */
i2c_send_stop();
/* fetch the last received byte */
buffer[index++] = I2C0->D;
return 0;
}
static uint32_t i2c_read(uint8_t reg)
{
// while ((I2C_SR2(i2c) & I2C_SR2_BUSY)) {
// }
i2c_send_start(I2C_PORT);
/* Wait for master mode selected */
while (!((I2C_SR1(I2C_PORT) & I2C_SR1_SB)
& (I2C_SR2(I2C_PORT) & (I2C_SR2_MSL | I2C_SR2_BUSY))));
i2c_send_7bit_address(I2C_PORT, SLAVE_ADDRESS, I2C_WRITE);
/* Waiting for address is transferred. */
while (!(I2C_SR1(I2C_PORT) & I2C_SR1_ADDR));
/* Cleaning ADDR condition sequence. */
uint32_t reg32 = I2C_SR2(I2C_PORT);
(void) reg32; /* unused */
/* Common stuff ABOVE HERE */
i2c_send_data(I2C_PORT, reg);
while (!(I2C_SR1(I2C_PORT) & (I2C_SR1_BTF)));
i2c_send_start(I2C_PORT);
/* Wait for master mode selected */
while (!((I2C_SR1(I2C_PORT) & I2C_SR1_SB)
& (I2C_SR2(I2C_PORT) & (I2C_SR2_MSL | I2C_SR2_BUSY))));
i2c_send_7bit_address(I2C_PORT, SLAVE_ADDRESS, I2C_READ);
/* Waiting for address is transferred. */
while (!(I2C_SR1(I2C_PORT) & I2C_SR1_ADDR));
i2c_disable_ack(I2C_PORT);
/* Cleaning ADDR condition sequence. */
reg32 = I2C_SR2(I2C_PORT);
(void) reg32; /* unused */
i2c_send_stop(I2C_PORT);
while (!(I2C_SR1(I2C_PORT) & I2C_SR1_RxNE));
uint32_t result = i2c_get_data(I2C_PORT);
i2c_enable_ack(I2C_PORT);
I2C_SR1(I2C_PORT) &= ~I2C_SR1_AF;
return result;
}
/*
* IRQ handler for I2C master. Handles transmission/reception.
*/
void _i2c_irq_handler(i2c_dev *dev) {
/* WTFs:
* - Where is I2C_MSG_10BIT_ADDR handled?
*/
i2c_msg *msg = dev->msg;
uint8 read = msg->flags & I2C_MSG_READ;
uint32 sr1 = dev->regs->SR1;
uint32 sr2 = dev->regs->SR2;
I2C_CRUMB(IRQ_ENTRY, sr1, sr2);
/*
* Reset timeout counter
*/
dev->timestamp = systick_uptime();
/*
* Add Slave support
*/
/* Check to see if MSL master slave bit is set */
if ((sr2 & I2C_SR2_MSL) != I2C_SR2_MSL) { /* 0 = slave mode 1 = master */
/* Check for address match */
if (sr1 & I2C_SR1_ADDR) {
/* Find out which address was matched */
/* Check the general call address first */
if (sr2 & I2C_SR2_GENCALL) {
dev->i2c_slave_msg->addr = 0;
}
/* We matched the secondary address */
else if (sr2 & I2C_SR2_DUALF) {
dev->i2c_slave_msg->addr = dev->regs->OAR2 & 0xFE;
}
/* We matched the primary address */
else if ((sr2 & I2C_SR2_DUALF) != I2C_SR2_DUALF) {
dev->i2c_slave_msg->addr = dev->regs->OAR1 & 0xFE;
}
/* Shouldn't get here */
else {
dev->i2c_slave_msg->addr = -1; /* uh oh */
}
/* if we have buffered io */
if ((dev->config_flags & I2C_SLAVE_USE_RX_BUFFER) ||
(dev->config_flags & I2C_SLAVE_USE_TX_BUFFER)) {
/* if receiving then this would be a repeated start
*
*if we have some bytes already
*/
if ((dev->state == I2C_STATE_SL_RX) &&
(dev->i2c_slave_msg->xferred > 0) &&
(dev->config_flags & I2C_SLAVE_USE_RX_BUFFER)) {
/* Call the callback with the contents of the data */
if (dev->i2c_slave_recv_callback != NULL) {
(*(dev->i2c_slave_recv_callback))(dev->i2c_slave_msg);
}
}
/* Reset the message back to defaults.
* We are starting a new message
*/
dev->i2c_slave_msg->flags = 0;
dev->i2c_slave_msg->length = 0;
dev->i2c_slave_msg->xferred = 0;
dev->msgs_left = 0;
dev->timestamp = systick_uptime();
/* We have been addressed with SLA+R so
* the master wants us to transmit
*/
if ((sr1 & I2C_SR1_TXE) &&
(dev->config_flags & I2C_SLAVE_USE_TX_BUFFER)) {
/* Call the transmit callback so it can populate the msg
* data with the bytes to go
*/
if (dev->i2c_slave_transmit_callback != NULL) {
(*(dev->i2c_slave_transmit_callback))(dev->i2c_slave_msg);
}
}
dev->state = I2C_STATE_BUSY;
}
sr1 = sr2 = 0;
}
/* EV3: Master requesting data from slave. Transmit a byte*/
if (sr1 & I2C_SR1_TXE) {
if (dev->config_flags & I2C_SLAVE_USE_TX_BUFFER) {
if (dev->i2c_slave_msg->xferred >= dev->i2c_slave_msg->length) {
/* End of the transmit buffer? If so we NACK */
i2c_disable_ack(dev);
/* We have to either issue a STOP or write something here.
* STOP here seems to screw up some masters,
* For now padding with 0
*/
i2c_write(dev, 0);
/*i2c_stop_condition(dev); // This is causing bus lockups way more than it should !? Seems some I2C master devices freak out here*/
}
else
{
/* NACk the last byte */
if (dev->i2c_slave_msg->xferred == dev->i2c_slave_msg->length-1) {
i2c_disable_ack(dev);
}
else {
i2c_enable_ack(dev);
}
i2c_write(dev, dev->i2c_slave_msg->data[dev->i2c_slave_msg->xferred++]);
}
}
else
{
/* Call the callback to get the data we need.
* The callback is expected to write using i2c_write(...)
* If the slave is going to terminate the transfer, this function should
* also do a NACK on the last byte!
*/
if (dev->i2c_slave_transmit_callback != NULL) (*(dev->i2c_slave_transmit_callback))(dev->i2c_slave_msg);
}
dev->state = I2C_STATE_BUSY;
sr1 = sr2 = 0;
}
/* EV2: Slave received data from a master. Get from DR */
if (sr1 & I2C_SR1_RXNE) {
if (dev->config_flags & I2C_SLAVE_USE_RX_BUFFER) {
/* Fill the buffer with the contents of the data register */
/* These is potential for buffer overflow here, so we should
* really store the size of the array. This is expensive in
* the ISR so left out for now. We must trust the implementor!
*/
dev->i2c_slave_msg->data[dev->i2c_slave_msg->xferred++] = dev->regs->DR;
dev->i2c_slave_msg->length++;
}
else {
/* Call the callback with the contents of the data */
dev->i2c_slave_msg->data[0] = dev->regs->DR;
if (dev->i2c_slave_recv_callback != NULL) (*(dev->i2c_slave_recv_callback))(dev->i2c_slave_msg);
}
dev->state = I2C_STATE_SL_RX;
sr1 = sr2 = 0;
}
/* EV4: Slave has detected a STOP condition on the bus */
if (sr1 & I2C_SR1_STOPF) {
dev->regs->CR1 |= I2C_CR1_PE;
if ((dev->config_flags & I2C_SLAVE_USE_RX_BUFFER) ||
(dev->config_flags & I2C_SLAVE_USE_TX_BUFFER)) {
/* The callback with the data will happen on a NACK of the last data byte.
* This is handled in the error IRQ (AF bit)
*/
/* Handle the case where the master misbehaves by sending no NACK */
if (dev->state != I2C_STATE_IDLE) {
if (dev->state == I2C_STATE_SL_RX) {
if (dev->i2c_slave_recv_callback != NULL) (*(dev->i2c_slave_recv_callback))(dev->i2c_slave_msg);
}
else {
if (dev->i2c_slave_transmit_callback != NULL) (*(dev->i2c_slave_transmit_callback))(dev->i2c_slave_msg);
}
}
}
sr1 = sr2 = 0;
dev->state = I2C_STATE_IDLE;
}
return;
}
/*
* EV5: Start condition sent
*/
if (sr1 & I2C_SR1_SB) {
msg->xferred = 0;
i2c_enable_irq(dev, I2C_IRQ_BUFFER);
/*
* Master receiver
*/
if (read) {
i2c_enable_ack(dev);
}
i2c_send_slave_addr(dev, msg->addr, read);
sr1 = sr2 = 0;
}
/*
* EV6: Slave address sent
*/
if (sr1 & I2C_SR1_ADDR) {
/*
* Special case event EV6_1 for master receiver.
* Generate NACK and restart/stop condition after ADDR
* is cleared.
*/
if (read) {
if (msg->length == 1) {
i2c_disable_ack(dev);
if (dev->msgs_left > 1) {
i2c_start_condition(dev);
I2C_CRUMB(RX_ADDR_START, 0, 0);
} else {
i2c_stop_condition(dev);
I2C_CRUMB(RX_ADDR_STOP, 0, 0);
}
}
} else {
/*
* Master transmitter: write first byte to fill shift
* register. We should get another TXE interrupt
* immediately to fill DR again.
*/
if (msg->length != 1) {
i2c_write(dev, msg->data[msg->xferred++]);
}
}
sr1 = sr2 = 0;
}
/*
* EV8: Master transmitter
* Transmit buffer empty, but we haven't finished transmitting the last
* byte written.
*/
if ((sr1 & I2C_SR1_TXE) && !(sr1 & I2C_SR1_BTF)) {
I2C_CRUMB(TXE_ONLY, 0, 0);
if (dev->msgs_left) {
i2c_write(dev, msg->data[msg->xferred++]);
if (msg->xferred == msg->length) {
/*
* End of this message. Turn off TXE/RXNE and wait for
* BTF to send repeated start or stop condition.
*/
i2c_disable_irq(dev, I2C_IRQ_BUFFER);
dev->msgs_left--;
}
} else {
/*
* This should be impossible...
*/
ASSERT(0);
}
sr1 = sr2 = 0;
}
/*
* EV8_2: Master transmitter
* Last byte sent, program repeated start/stop
*/
if ((sr1 & I2C_SR1_TXE) && (sr1 & I2C_SR1_BTF)) {
I2C_CRUMB(TXE_BTF, 0, 0);
if (dev->msgs_left) {
I2C_CRUMB(TEST, 0, 0);
/*
* Repeated start insanity: We can't disable ITEVTEN or else SB
* won't interrupt, but if we don't disable ITEVTEN, BTF will
* continually interrupt us. What the f**k ST?
*/
i2c_start_condition(dev);
while (!(dev->regs->SR1 & I2C_SR1_SB))
;
dev->msg++;
} else {
i2c_stop_condition(dev);
/*
* Turn off event interrupts to keep BTF from firing until
* the end of the stop condition. Why on earth they didn't
* have a start/stop condition request clear BTF is beyond
* me.
*/
i2c_disable_irq(dev, I2C_IRQ_EVENT);
I2C_CRUMB(STOP_SENT, 0, 0);
dev->state = I2C_STATE_XFER_DONE;
}
sr1 = sr2 = 0;
}
/*
* EV7: Master Receiver
*/
if (sr1 & I2C_SR1_RXNE) {
I2C_CRUMB(RXNE_ONLY, 0, 0);
msg->data[msg->xferred++] = dev->regs->DR;
/*
* EV7_1: Second to last byte in the reception? Set NACK and generate
* stop/restart condition in time for the last byte. We'll get one more
* RXNE interrupt before shutting things down.
*/
if (msg->xferred == (msg->length - 1)) {
i2c_disable_ack(dev);
if (dev->msgs_left > 2) {
i2c_start_condition(dev);
I2C_CRUMB(RXNE_START_SENT, 0, 0);
} else {
i2c_stop_condition(dev);
I2C_CRUMB(RXNE_STOP_SENT, 0, 0);
}
} else if (msg->xferred == msg->length) {
dev->msgs_left--;
if (dev->msgs_left == 0) {
/*
* We're done.
*/
I2C_CRUMB(RXNE_DONE, 0, 0);
dev->state = I2C_STATE_XFER_DONE;
} else {
dev->msg++;
}
}
}
}
// Doc ID 13902 Rev 11 p 712/1072
// Transfer Sequence Diagram for Master Receiver for N>2
static inline enum STMI2CSubTransactionStatus stmi2c_readmany(uint32_t i2c, struct i2c_periph *periph, struct i2c_transaction *trans)
{
uint16_t SR1 = I2C_SR1(i2c);
// Start Condition Was Just Generated
if (BIT_X_IS_SET_IN_REG( I2C_SR1_SB, SR1 ) )
{
i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
// The first data byte will be acked in read many so the slave knows it should send more
i2c_nack_current(i2c);
i2c_enable_ack(i2c);
// Clear the SB flag
i2c_send_data(i2c, trans->slave_addr | 0x01);
// Document the current Status
periph->status = I2CAddrRdSent;
}
// Address Was Sent
else if (BIT_X_IS_SET_IN_REG(I2C_SR1_ADDR, SR1) )
{
periph->idx_buf = 0;
// Enable RXNE: receive an interrupt any time a byte is available
// only enable if MORE than 3 bytes need to be read
if (periph->idx_buf < (trans->len_r - 3))
{
i2c_enable_interrupt(i2c, I2C_CR2_ITBUFEN);
}
// ACK is still on to get more DATA
// Read SR2 to clear the ADDR (next byte will start arriving)
uint16_t SR2 __attribute__ ((unused)) = I2C_SR2(i2c);
// Document the current Status
periph->status = I2CReadingByte;
}
// one or more bytes are available AND we were interested in Buffer interrupts
else if ( (BIT_X_IS_SET_IN_REG(I2C_SR1_RxNE, SR1) ) && (BIT_X_IS_SET_IN_REG(I2C_CR2_ITBUFEN, I2C_CR2(i2c))) )
{
// read byte until 3 bytes remain to be read (e.g. len_r = 6, -> idx=3 means idx 3,4,5 = 3 remain to be read
if (periph->idx_buf < (trans->len_r - 3))
{
trans->buf[periph->idx_buf] = I2C_DR(i2c);
periph->idx_buf ++;
}
// from : 3bytes -> last byte: do nothing
//
// finally: this was the last byte
else if (periph->idx_buf >= (trans->len_r - 1))
{
i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
// Last Value
trans->buf[periph->idx_buf] = i2c_get_data(i2c);
periph->idx_buf ++;
// We got all the results
trans->status = I2CTransSuccess;
return STMI2C_SubTra_Ready_StopRequested;
}
// Check for end of transaction: start waiting for BTF instead of RXNE
if (periph->idx_buf < (trans->len_r - 3))
{
i2c_enable_interrupt(i2c, I2C_CR2_ITBUFEN);
}
else // idx >= len-3: there are 3 bytes to be read
{
// We want to halt I2C to have sufficient time to clear ACK, so:
// Stop listening to RXNE as it will be triggered infinitely since we did not empty the buffer
// on the next (second in buffer) received byte BTF will be set (buffer full and I2C halted)
i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
}
}
// Buffer is full while this was not a RXNE interrupt
else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BTF, SR1) )
{
// Now the shift register and data register contain data(n-2) and data(n-1)
// And I2C is halted so we have time
// --- Make absolutely sure the next 2 I2C actions are performed with no delay
__I2C_REG_CRITICAL_ZONE_START;
// First we clear the ACK while the SCL is held low by BTF
i2c_disable_ack(i2c);
// Now that ACK is cleared we read one byte: instantly the last byte is being clocked in...
trans->buf[periph->idx_buf] = i2c_get_data(i2c);
periph->idx_buf ++;
// Now the last byte is being clocked. Stop in MUST be set BEFORE the transfer of the last byte is complete
PPRZ_I2C_SEND_STOP(i2c);
__I2C_REG_CRITICAL_ZONE_STOP;
// --- end of critical zone -----------
// Document the current Status
periph->status = I2CStopRequested;
// read the byte2 we had in the buffer (BTF means 2 bytes available)
trans->buf[periph->idx_buf] = i2c_get_data(i2c);
periph->idx_buf ++;
// Ask for an interrupt to read the last byte (which is normally still busy now)
// The last byte will be received with RXNE
i2c_enable_interrupt(i2c, I2C_CR2_ITBUFEN);
}
else // Event Logic Error
{
return STMI2C_SubTra_Error;
}
return STMI2C_SubTra_Busy;
}
// Doc ID 13902 Rev 11 p 713/1072
// Transfer Sequence Diagram for Master Receiver for N=2
static inline enum STMI2CSubTransactionStatus stmi2c_read2(uint32_t i2c, struct i2c_periph *periph, struct i2c_transaction *trans)
{
uint16_t SR1 = I2C_SR1(i2c);
// Start Condition Was Just Generated
if (BIT_X_IS_SET_IN_REG( I2C_SR1_SB, SR1 ) )
{
// according to the datasheet: instantly shedule a NAK on the second received byte:
i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
i2c_enable_ack(i2c);
i2c_nack_next(i2c);
i2c_send_data(i2c, trans->slave_addr | 0x01);
// Document the current Status
periph->status = I2CAddrRdSent;
}
// Address Was Sent
else if (BIT_X_IS_SET_IN_REG(I2C_SR1_ADDR, SR1) )
{
// --- make absolutely sure this command is not delayed too much after the previous:
// --- the NAK bits must be set before the first byte arrived: allow other interrupts here
__I2C_REG_CRITICAL_ZONE_START;
// if transfer of DR was finished already then we will get too many bytes
// BEFORE clearing ACK, read SR2 to clear the ADDR (next byte will start arriving)
// clearing ACK after the byte transfer has already started will NACK the next (2nd)
uint16_t SR2 __attribute__ ((unused)) = I2C_SR2(i2c);
// NOT First Clear the ACK bit but only AFTER clearing ADDR
i2c_disable_ack(i2c);
// Disable the RXNE and wait for BTF
i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
__I2C_REG_CRITICAL_ZONE_STOP;
// --- end of critical zone -----------
// We do not set the RxE but wait for both bytes to arrive using BTF
// Document the current Status
periph->status = I2CReadingByte;
}
// Receive buffer if full, master is halted: BTF
else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BTF, SR1) )
{
// Stop condition MUST be set BEFORE reading the DR
// otherwise since there is new buffer space a new byte will be read
PPRZ_I2C_SEND_STOP(i2c);
// Document the current Status
periph->status = I2CStopRequested;
trans->buf[0] = I2C_DR(i2c);
trans->buf[1] = I2C_DR(i2c);
// We got all the results
trans->status = I2CTransSuccess;
return STMI2C_SubTra_Ready_StopRequested;
}
else // Event Logic Error
{
return STMI2C_SubTra_Error;
}
return STMI2C_SubTra_Busy;
}
/**
* @brief IRQ handler for I2C master. Handles transmission/reception.
* @param dev I2C device
*/
static void i2c_irq_handler(i2c_dev *dev) {
i2c_msg *msg = dev->msg;
uint8 read = msg->flags & I2C_MSG_READ;
uint32 sr1 = dev->regs->SR1;
uint32 sr2 = dev->regs->SR2;
I2C_CRUMB(IRQ_ENTRY, sr1, sr2);
/*
* Reset timeout counter
*/
dev->timestamp = systick_uptime();
/*
* EV5: Start condition sent
*/
if (sr1 & I2C_SR1_SB) {
msg->xferred = 0;
i2c_enable_irq(dev, I2C_IRQ_BUFFER);
/*
* Master receiver
*/
if (read) {
i2c_enable_ack(dev);
}
i2c_send_slave_addr(dev, msg->addr, read);
sr1 = sr2 = 0;
}
/*
* EV6: Slave address sent
*/
if (sr1 & I2C_SR1_ADDR) {
/*
* Special case event EV6_1 for master receiver.
* Generate NACK and restart/stop condition after ADDR
* is cleared.
*/
if (read) {
if (msg->length == 1) {
i2c_disable_ack(dev);
if (dev->msgs_left > 1) {
i2c_start_condition(dev);
I2C_CRUMB(RX_ADDR_START, 0, 0);
} else {
i2c_stop_condition(dev);
I2C_CRUMB(RX_ADDR_STOP, 0, 0);
}
}
} else {
/*
* Master transmitter: write first byte to fill shift
* register. We should get another TXE interrupt
* immediately to fill DR again.
*/
if (msg->length != 1) {
i2c_write(dev, msg->data[msg->xferred++]);
}
}
sr1 = sr2 = 0;
}
/*
* EV8: Master transmitter
* Transmit buffer empty, but we haven't finished transmitting the last
* byte written.
*/
if ((sr1 & I2C_SR1_TXE) && !(sr1 & I2C_SR1_BTF)) {
I2C_CRUMB(TXE_ONLY, 0, 0);
if (dev->msgs_left) {
i2c_write(dev, msg->data[msg->xferred++]);
if (msg->xferred == msg->length) {
/*
* End of this message. Turn off TXE/RXNE and wait for
* BTF to send repeated start or stop condition.
*/
i2c_disable_irq(dev, I2C_IRQ_BUFFER);
dev->msgs_left--;
}
} else {
/*
* This should be impossible...
*/
throb();
}
sr1 = sr2 = 0;
}
/*
* EV8_2: Master transmitter
* Last byte sent, program repeated start/stop
*/
if ((sr1 & I2C_SR1_TXE) && (sr1 & I2C_SR1_BTF)) {
I2C_CRUMB(TXE_BTF, 0, 0);
if (dev->msgs_left) {
I2C_CRUMB(TEST, 0, 0);
/*
* Repeated start insanity: We can't disable ITEVTEN or else SB
* won't interrupt, but if we don't disable ITEVTEN, BTF will
* continually interrupt us. What the f**k ST?
*/
i2c_start_condition(dev);
while (!(dev->regs->SR1 & I2C_SR1_SB))
;
dev->msg++;
} else {
i2c_stop_condition(dev);
/*
* Turn off event interrupts to keep BTF from firing until
* the end of the stop condition. Why on earth they didn't
* have a start/stop condition request clear BTF is beyond
* me.
*/
i2c_disable_irq(dev, I2C_IRQ_EVENT);
I2C_CRUMB(STOP_SENT, 0, 0);
dev->state = I2C_STATE_XFER_DONE;
}
sr1 = sr2 = 0;
}
/*
* EV7: Master Receiver
*/
if (sr1 & I2C_SR1_RXNE) {
I2C_CRUMB(RXNE_ONLY, 0, 0);
msg->data[msg->xferred++] = dev->regs->DR;
/*
* EV7_1: Second to last byte in the reception? Set NACK and generate
* stop/restart condition in time for the last byte. We'll get one more
* RXNE interrupt before shutting things down.
*/
if (msg->xferred == (msg->length - 1)) {
i2c_disable_ack(dev);
if (dev->msgs_left > 2) {
i2c_start_condition(dev);
I2C_CRUMB(RXNE_START_SENT, 0, 0);
} else {
i2c_stop_condition(dev);
I2C_CRUMB(RXNE_STOP_SENT, 0, 0);
}
} else if (msg->xferred == msg->length) {
dev->msgs_left--;
if (dev->msgs_left == 0) {
/*
* We're done.
*/
I2C_CRUMB(RXNE_DONE, 0, 0);
dev->state = I2C_STATE_XFER_DONE;
} else {
dev->msg++;
}
}
}
}
static void setup_i2c_port(enum I2C_FREQ I2C_speed)
{
// Disable I2C if it happens to be enabled
i2c_peripheral_disable(I2C_PORT);
dma_channel_reset(I2C_TX_DMA, I2C_TX_DMA_CHANNEL);
i2c_disable_interrupt(I2C_PORT, (I2C_CR2_ITEVTEN | I2C_CR2_ITERREN));
DISABLE_I2C_INTERRUPT();
reset_i2c_pins();
// set: Source, Destination, and Amount (DMA channel must be disabled)
dma_set_peripheral_address(I2C_TX_DMA, I2C_TX_DMA_CHANNEL, (uint32_t)&I2C_DR(I2C_PORT));
dma_set_memory_address(I2C_TX_DMA, I2C_TX_DMA_CHANNEL, 0);
dma_set_number_of_data(I2C_TX_DMA, I2C_TX_DMA_CHANNEL, 0);
// set the DMA Configuration (DMA_CCRx)
// (BIT 14) mem2mem_mode disabled
dma_set_priority(I2C_TX_DMA, I2C_TX_DMA_CHANNEL, DMA_CCR_PL_HIGH); // (BIT 12:13)
dma_set_memory_size(I2C_TX_DMA, I2C_TX_DMA_CHANNEL, DMA_CCR_MSIZE_8BIT); // (BIT 10:11)
dma_set_peripheral_size(I2C_TX_DMA, I2C_TX_DMA_CHANNEL, DMA_CCR_PSIZE_8BIT); // (BIT 8:9)
dma_enable_memory_increment_mode(I2C_TX_DMA, I2C_TX_DMA_CHANNEL); // (BIT 7)
dma_disable_peripheral_increment_mode(I2C_TX_DMA, I2C_TX_DMA_CHANNEL); // (BIT 6)
// (BIT 5) Circular mode is disabled
dma_set_read_from_memory(I2C_TX_DMA, I2C_TX_DMA_CHANNEL); // (BIT 4)
dma_enable_transfer_error_interrupt(I2C_TX_DMA, I2C_TX_DMA_CHANNEL); // (BIT 3)
dma_disable_half_transfer_interrupt(I2C_TX_DMA, I2C_TX_DMA_CHANNEL); // (BIT 2)
dma_enable_transfer_complete_interrupt(I2C_TX_DMA, I2C_TX_DMA_CHANNEL); // (BIT 1)
// This is the slave address when not transmitting data
i2c_set_own_7bit_slave_address(I2C_PORT, 0x32);
// do not respond to the specified slave address
i2c_disable_ack(I2C_PORT);
// Use DMA to send I2C data
i2c_enable_dma(I2C_PORT);
// set which interrupts I2C uses
i2c_enable_interrupt(I2C_PORT, (I2C_CR2_ITEVTEN | I2C_CR2_ITERREN));
// APB1 is running at 36MHz = T(PCLK1) = 1/36000000 sec.
i2c_set_clock_frequency(I2C_PORT, I2C_CR2_FREQ_36MHZ);
// Set up the hardware for the particular speed
switch (I2C_speed) {
// Values found on Internet for the I2C standard
// STANDARD : SCL max rise time = 1000ns = 1000/1000000000 sec
// FAST : SCL max rise time = 300ns = 300/1000000000 sec
//
// DATASHEET Function:
// TRISE = (T(MAX_SCL_RISE) / T(PCLK1)) + 1
//
// DATASHEET Functions:
// STANDARD :
// T(high) = CCR * T(PCLK1)
// T(low) = CCR * T(PCLK1)
// FAST (DUTY=I2C_CCR_DUTY_DIV2)
// T(high) = CCR * T(PCLK1)
// T(low) = 2 * CCR * T(PCLK1)
// FAST (DUTY=I2C_CCR_DUTY_16_DIV_9) [To reach 400KHz]
// T(high) = 9 * CCR * T(PCLK1)
// T(low) = 16 * CCR * T(PCLK1)
//
// I2C PERIOD:
// STANDARD
// PERIOD = T(high) + T(low) = (2 * CCR * T(PCLK1))
// FAST (DUTY=I2C_CCR_DUTY_DIV2)
// PERIOD = T(high) + T(low) = (3 * CCR * T(PCLK1))
// FAST (DUTY=I2C_CCR_DUTY_16_DIV_9)
// PERIOD = T(high) + T(low) = (25 * CCR * T(PCLK1))
case I2C_400KHz:
// I2C PERIOD: 400KHz = 400000Hz = 1/400000 sec.
i2c_set_fast_mode(I2C_PORT);
// I2C_CCR_DUTY_DIV2 or I2C_CCR_DUTY_16_DIV_9
i2c_set_dutycycle(I2C_PORT, I2C_CCR_DUTY_16_DIV_9);
// CCR = PERIOD / (25 * T(PCLK1))
// CCR = (1/400000) / (25/36000000) = 18/5 = 3.6
// CCR = 4 => I2C PERIOD = 360kHz
// CCR = 3 => I2C PERIOD = 480kHz
i2c_set_ccr(I2C_PORT, 4); // Only fast mode can have a value less than 0x04
// TRISE = ( (300/1000000000) / (1/36000000) ) + 1 = 59/5 = 11.8
// TRISE = 12 => SCL max rise time ~= 305.555ns
// TRISE = 11 => SCL max rise time ~= 277.777ns
i2c_set_trise(I2C_PORT, 11);
break;
case I2C_100KHz:
// I2C PERIOD: 100KHz = 100000Hz = 1/100000 sec.
i2c_set_standard_mode(I2C_PORT);
// I2C_CCR_DUTY_DIV2 or I2C_CCR_DUTY_16_DIV_9
i2c_set_dutycycle(I2C_PORT, I2C_CCR_DUTY_DIV2);
// CCR = PERIOD / (2 * T(PCLK1))
// CCR = (1/100000) / (2/36000000) = 180
i2c_set_ccr(I2C_PORT, 180);
// TRISE = ( (1000/1000000000) / (1/36000000) ) + 1 = 37
i2c_set_trise(I2C_PORT, 37);
break;
case I2C_53KHz:
// ~= 52.91kHz is the slowest I could get to work
// CCR value of 341 works but not 342 or higher
case I2C_50KHz:
default:
// I2C PERIOD: 50KHz = 50000Hz = 1/50000 sec.
i2c_set_standard_mode(I2C_PORT);
// I2C_CCR_DUTY_DIV2 or I2C_CCR_DUTY_16_DIV_9
i2c_set_dutycycle(I2C_PORT, I2C_CCR_DUTY_DIV2);
// CCR = PERIOD / (2 * T(PCLK1))
// CCR = (1/50000) / (2/36000000) = 360
// (341 works but not 342 or higher)
i2c_set_ccr(I2C_PORT, 341);
// TRISE = ( (1000/1000000000) / (1/36000000) ) + 1 = 37
i2c_set_trise(I2C_PORT, 37);
break;
}
i2c_peripheral_enable(I2C_PORT);
// set the priorities for the interrupts
nvic_set_priority(I2C_EV_IRQ, IRQ_PRI_I2C);
nvic_set_priority(I2C_ER_IRQ, IRQ_PRI_ER_I2C);
nvic_set_priority(I2C_DMA_IRQ, IRQ_PRI_DMA_I2C);
}
