void i2c_reg_write(uint8_t addr, uint8_t reg, uint8_t val)
{
#ifdef CONFIG_8xx
/* MPC8xx needs this. Maybe one day we can get rid of it. */
/* maybe it is now the time for it ... */
i2c_set_bus_num(i2c_get_bus_num());
#endif
#ifdef DEBUG
printf("%s: bus=%d addr=0x%02x, reg=0x%02x, val=0x%02x\n",
__func__, i2c_get_bus_num(), addr, reg, val);
#endif
i2c_write(addr, reg, 1, &val, 1);
}
static int eeprom_bus_read (unsigned dev_addr, unsigned offset, uchar *buffer,
unsigned cnt)
{
int rcode;
#if defined(CONFIG_I2C_ENV_EEPROM_BUS)
int old_bus = i2c_get_bus_num();
if (gd->flags & GD_FLG_RELOC) {
if (env_eeprom_bus == -1) {
I2C_MUX_DEVICE *dev = NULL;
dev = i2c_mux_ident_muxstring(
(uchar *)CONFIG_I2C_ENV_EEPROM_BUS);
if (dev != NULL) {
env_eeprom_bus = dev->busid;
} else
printf ("error adding env eeprom bus.\n");
}
if (old_bus != env_eeprom_bus) {
i2c_set_bus_num(env_eeprom_bus);
old_bus = env_eeprom_bus;
}
} else {
rcode = i2c_mux_ident_muxstring_f(
(uchar *)CONFIG_I2C_ENV_EEPROM_BUS);
}
#endif
rcode = eeprom_read (dev_addr, offset, buffer, cnt);
#if defined(CONFIG_I2C_ENV_EEPROM_BUS)
if (old_bus != env_eeprom_bus)
i2c_set_bus_num(old_bus);
#endif
return rcode;
}
/* program the regulator (MC34VR500) to support deep sleep */
void ls1twr_program_regulator(void)
{
unsigned int i2c_bus;
u8 i2c_device_id;
#define LS1TWR_I2C_BUS_MC34VR500 1
#define MC34VR500_ADDR 0x8
#define MC34VR500_DEVICEID 0x4
#define MC34VR500_DEVICEID_MASK 0x0f
i2c_bus = i2c_get_bus_num();
i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500);
i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) &
MC34VR500_DEVICEID_MASK;
if (i2c_device_id != MC34VR500_DEVICEID) {
printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
return;
}
i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4);
i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4);
i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38);
i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37);
i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30);
i2c_set_bus_num(i2c_bus);
}
/**
* read_eeprom - read the EEPROM into memory
*/
static int read_eeprom(void)
{
int ret;
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
unsigned int bus;
#endif
if (has_been_read)
return 0;
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
bus = i2c_get_bus_num();
i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
#endif
ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
(void *)&e, sizeof(e));
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
i2c_set_bus_num(bus);
#endif
#ifdef DEBUG
show_eeprom();
#endif
has_been_read = (ret == 0) ? 1 : 0;
return ret;
}
/**
* prog_eeprom - write the EEPROM from memory
*/
static int prog_eeprom(void)
{
int ret = 0;
int i;
void *p;
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
unsigned int bus;
#endif
/* Set the reserved values to 0xFF */
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
e.res_0 = 0xFF;
memset(e.res_1, 0xFF, sizeof(e.res_1));
#else
memset(e.res_0, 0xFF, sizeof(e.res_0));
#endif
update_crc();
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
bus = i2c_get_bus_num();
i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
#endif
/*
* The AT24C02 datasheet says that data can only be written in page
* mode, which means 8 bytes at a time, and it takes up to 5ms to
* complete a given write.
*/
for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) {
ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
p, min((sizeof(e) - i), 8));
if (ret)
break;
udelay(5000); /* 5ms write cycle timing */
}
if (!ret) {
/* Verify the write by reading back the EEPROM and comparing */
struct eeprom e2;
ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (void *)&e2, sizeof(e2));
if (!ret && memcmp(&e, &e2, sizeof(e)))
ret = -1;
}
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
i2c_set_bus_num(bus);
#endif
if (ret) {
printf("Programming failed.\n");
has_been_read = 0;
return -1;
}
printf("Programming passed.\n");
return 0;
}
uint8_t i2c_reg_read(uint8_t addr, uint8_t reg)
{
uint8_t buf;
#ifdef CONFIG_8xx
/* MPC8xx needs this. Maybe one day we can get rid of it. */
/* maybe it is now the time for it ... */
i2c_set_bus_num(i2c_get_bus_num());
#endif
i2c_read(addr, reg, 1, &buf, 1);
#ifdef DEBUG
printf("%s: bus=%d addr=0x%02x, reg=0x%02x, val=0x%02x\n",
__func__, i2c_get_bus_num(), addr, reg, buf);
#endif
return buf;
}
int max77686_volsetting(enum max77686_regnum reg, unsigned int volt,
int enable, int volt_units)
{
int old_bus = i2c_get_bus_num();
int ret;
i2c_set_bus_num(0);
ret = max77686_do_volsetting(reg, volt, enable, volt_units);
i2c_set_bus_num(old_bus);
return ret;
}
int s5m8767_volsetting(enum s5m8767_regnum reg, unsigned int volt,
int enable, int volt_units)
{
int old_bus = i2c_get_bus_num();
int ret;
i2c_set_bus_num(0);
ret = s5m8767_do_volsetting(reg, volt, enable, volt_units);
i2c_set_bus_num(old_bus);
return ret;
}
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
unsigned int orig_bus = i2c_get_bus_num();
u8 i2c_data;
i2c_set_bus_num(1);
if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0,
1, &i2c_data, sizeof(i2c_data)) == 0) {
if (i2c_data & 0x2)
puts("NOR Flash Bank : Secondary\n");
else
puts("NOR Flash Bank : Primary\n");
if (i2c_data & 0x1) {
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
puts("SD/MMC : 8-bit Mode\n");
puts("eSPI : Disabled\n");
} else {
puts("SD/MMC : 4-bit Mode\n");
puts("eSPI : Enabled\n");
}
} else {
puts("Failed reading I2C Chip 0x18 on bus 1\n");
}
i2c_set_bus_num(orig_bus);
/*
* Remap Boot flash region to caching-inhibited
* so that flash can be erased properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_16M, 1);
rtc_reset();
return 0;
}
static int tpm_deselect(void)
{
int ret;
if (tpm.old_bus != i2c_get_bus_num()) {
ret = i2c_set_bus_num(tpm.old_bus);
if (ret) {
debug("%s: Fail to restore i2c bus %d\n",
__func__, tpm.old_bus);
return -1;
}
}
tpm.old_bus = -1;
return 0;
}
static int tpm_select(void)
{
int ret;
tpm.old_bus = i2c_get_bus_num();
if (tpm.old_bus != tpm.i2c_bus) {
ret = i2c_set_bus_num(tpm.i2c_bus);
if (ret) {
debug("%s: Fail to set i2c bus %d\n", __func__,
tpm.i2c_bus);
return -1;
}
}
return 0;
}
static int eeprom_bus_write (unsigned dev_addr, unsigned offset, uchar *buffer,
unsigned cnt)
{
int rcode;
#if defined(CONFIG_I2C_ENV_EEPROM_BUS)
int old_bus = i2c_get_bus_num();
rcode = i2c_mux_ident_muxstring_f((uchar *)CONFIG_I2C_ENV_EEPROM_BUS);
#endif
rcode = eeprom_write (dev_addr, offset, buffer, cnt);
#if defined(CONFIG_I2C_ENV_EEPROM_BUS)
i2c_set_bus_num(old_bus);
#endif
return rcode;
}
/**
* ti_i2c_eeprom_read - Read data from an EEPROM
* @dev_addr: The device address of the EEPROM
* @offset: Offset to start reading in the EEPROM
* @ep: Pointer to a buffer to read into
* @epsize: Size of buffer
*
* Return: 0 on success or corresponding result of i2c_read
*/
static int __maybe_unused ti_i2c_eeprom_read(int dev_addr, int offset,
uchar *ep, int epsize)
{
int bus_num, rc, alen;
bus_num = i2c_get_bus_num();
alen = 2;
rc = ti_i2c_set_alen(bus_num, dev_addr, alen);
if (rc)
return rc;
return i2c_read(dev_addr, offset, alen, ep, epsize);
}
int get_multi_sda_pin(void)
{
unsigned int bus = i2c_get_bus_num();
switch (bus) {
case I2C_0:
return CONFIG_SOFT_I2C_I2C5_SDA;
case I2C_1:
return CONFIG_SOFT_I2C_I2C9_SDA;
default:
printf("I2C_%d not supported!\n", bus);
};
return 0;
}
static int cl_eeprom_read(uint offset, uchar *buf, int len)
{
int res;
unsigned int current_i2c_bus = i2c_get_bus_num();
res = i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
if (res < 0)
return res;
res = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, offset,
CONFIG_SYS_I2C_EEPROM_ADDR_LEN, buf, len);
i2c_set_bus_num(current_i2c_bus);
return res;
}
static int tps65090_deselect(void)
{
int ret;
if (config.old_bus != i2c_get_bus_num()) {
ret = i2c_set_bus_num(config.old_bus);
debug("%s: Select bus %d\n", __func__, config.old_bus);
if (ret) {
debug("%s: Cannot restore i2c bus, err %d\n",
__func__, ret);
return -1;
}
}
config.old_bus = -1;
return 0;
}
/* Initialize Top Avatar, send initial Vout PMBus command to Top Avatar */
int srss_tps544_init(u32 vid, u32 i2c_bus, u8 i2c_addr)
{
/* Vout in PMBus format, Vout (Volt) = vout_pmbus[vid]/512,
* e.g. vid = 0, Vout = 0x0166 / 512 = 0.699 (Volt) */
uchar vout_pmbus[64][2] = {
{0x66, 0x1}, {0x69, 0x1}, {0x6d, 0x1}, {0x70, 0x1},
{0x73, 0x1}, {0x76, 0x1}, {0x79, 0x1}, {0x7d, 0x1},
{0x80, 0x1}, {0x84, 0x1}, {0x87, 0x1}, {0x8a, 0x1},
{0x8d, 0x1}, {0x90, 0x1}, {0x94, 0x1}, {0x97, 0x1},
{0x9a, 0x1}, {0x9e, 0x1}, {0xa1, 0x1}, {0xa4, 0x1},
{0xa7, 0x1}, {0xab, 0x1}, {0xae, 0x1}, {0xb1, 0x1},
{0xb5, 0x1}, {0xb8, 0x1}, {0xbb, 0x1}, {0xbe, 0x1},
{0xc2, 0x1}, {0xc5, 0x1}, {0xc8, 0x1}, {0xcb, 0x1},
{0xcf, 0x1}, {0xd2, 0x1}, {0xd6, 0x1}, {0xd9, 0x1},
{0xdc, 0x1}, {0xdf, 0x1}, {0xe2, 0x1}, {0xe6, 0x1},
{0xe9, 0x1}, {0xec, 0x1}, {0xf0, 0x1}, {0xf3, 0x1},
{0xf6, 0x1}, {0xf9, 0x1}, {0xfc, 0x1}, {0x00, 0x2},
{0x03, 0x2}, {0x07, 0x2}, {0x0a, 0x2}, {0x0d, 0x2},
{0x10, 0x2}, {0x13, 0x2}, {0x17, 0x2}, {0x1a, 0x2},
{0x1d, 0x2}, {0x21, 0x2}, {0x24, 0x2}, {0x27, 0x2},
{0x2b, 0x2}, {0x2e, 0x2}, {0x31, 0x2}, {0x34, 0x2}
};
uchar on_off_config[] = {0x2,};
uchar vout_ov_fault_limit = {0x33, 0x02}; /* 1.1 V, 0x0233/512 */
uchar vout_ov_warn_limit = {0x29, 0x02}; /* 1.08 V, 0x0229/512 */
u32 old_bus;
old_bus = i2c_get_bus_num();
i2c_set_bus_num(i2c_bus);
if (i2c_write(i2c_addr, PMBUS_ON_OFF_CONFIG, 1, on_off_config, 1) != 0)
goto err;
if (i2c_write(i2c_addr, PMBUS_VOUT_OV_FAULT_LIMIT, 1,
vout_ov_fault_limit, 2) != 0)
goto err;
if (i2c_write(i2c_addr, PMBUS_VOUT_OV_WARN_LIMIT, 1,
vout_ov_warn_limit, 2) != 0)
goto err;
if (i2c_write(i2c_addr, PMBUS_VOUT_COMMAND, 1, vout_pmbus[vid], 2) != 0)
goto err;
i2c_set_bus_num(old_bus);
return 0;
err:
printf("tps544_init i2c write error\n");
i2c_set_bus_num(old_bus);
return -1;
}
/**
* prog_eeprom - write the EEPROM from memory
*/
static int prog_eeprom(void)
{
int ret, i, length;
unsigned int crc;
void *p;
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
unsigned int bus;
#endif
/* Set the reserved values to 0xFF */
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
e.res_0 = 0xFF;
memset(e.res_1, 0xFF, sizeof(e.res_1));
#else
memset(e.res_0, 0xFF, sizeof(e.res_0));
#endif
length = sizeof(e);
crc = crc32(0, (void *)&e, length - 4);
e.crc = cpu_to_be32(crc);
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
bus = i2c_get_bus_num();
i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
#endif
for (i = 0, p = &e; i < length; i += 8, p += 8) {
ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
p, min((length - i), 8));
if (ret)
break;
udelay(5000); /* 5ms write cycle timing */
}
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
i2c_set_bus_num(bus);
#endif
if (ret) {
printf("Programming failed.\n");
return -1;
}
printf("Programming passed.\n");
return 0;
}
/*
* The P2020COME board has a STMicro M41ST85W RTC/watchdog
* at i2c bus 1 address 0x68.
*/
static void start_rtc(void)
{
unsigned int bus = i2c_get_bus_num();
if (i2c_set_bus_num(M41ST85W_I2C_BUS)) {
M41ST85W_ERROR("unable to set i2c bus\n");
goto out;
}
/* ensure ST (stop) and HT (halt update) bits are cleared */
m41st85w_clear_bit(M41ST85W_REG_SEC2, M41ST85W_REG_SEC2_ST, "ST");
m41st85w_clear_bit(M41ST85W_REG_ALHOUR, M41ST85W_REG_ALHOUR_HT, "HT");
out:
/* reset the i2c bus */
i2c_set_bus_num(bus);
}
static int tps65090_select(void)
{
int ret;
config.old_bus = i2c_get_bus_num();
if (config.old_bus != config.bus) {
debug("%s: Select bus %d\n", __func__, config.bus);
ret = i2c_set_bus_num(config.bus);
if (ret) {
debug("%s: Cannot select TPS65090, err %d\n",
__func__, ret);
return -1;
}
}
return 0;
}
/**
* prog_eeprom - write the EEPROM from memory
*/
static int prog_eeprom(void)
{
int ret = 0;
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
unsigned int bus;
#endif
update_crc();
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
bus = i2c_get_bus_num();
i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
#endif
ret = eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
(uchar *)&e, sizeof(e));
if (!ret) {
/* Verify the write by reading back the EEPROM and comparing */
struct eeprom e2;
#ifdef DEBUG
printf("%s verifying...\n", __func__);
#endif
ret = eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
(uchar *)&e2, sizeof(e2));
if (!ret && memcmp(&e, &e2, sizeof(e)))
ret = -1;
}
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
i2c_set_bus_num(bus);
#endif
if (ret) {
printf("Programming failed.\n");
has_been_read = 0;
return -1;
}
printf("Programming passed.\n");
return 0;
}
/**
* prog_eeprom - write the EEPROM from memory
*/
static int prog_eeprom(void)
{
int ret = 0; /* shut up gcc */
int i;
void *p;
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
unsigned int bus;
#endif
/* Set the reserved values to 0xFF */
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
e.res_0 = 0xFF;
memset(e.res_1, 0xFF, sizeof(e.res_1));
#else
memset(e.res_0, 0xFF, sizeof(e.res_0));
#endif
update_crc();
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
bus = i2c_get_bus_num();
i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
#endif
for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) {
ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
p, min((sizeof(e) - i), 8));
if (ret)
break;
udelay(5000); /* 5ms write cycle timing */
}
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
i2c_set_bus_num(bus);
#endif
if (ret) {
printf("Programming failed.\n");
return -1;
}
printf("Programming passed.\n");
return 0;
}
static int eeprom_bus_read(unsigned dev_addr, unsigned offset,
uchar *buffer, unsigned cnt)
{
int rcode;
#if defined(CONFIG_I2C_ENV_EEPROM_BUS)
int old_bus = i2c_get_bus_num();
if (old_bus != CONFIG_I2C_ENV_EEPROM_BUS)
i2c_set_bus_num(CONFIG_I2C_ENV_EEPROM_BUS);
#endif
rcode = eeprom_read(dev_addr, offset, buffer, cnt);
#if defined(CONFIG_I2C_ENV_EEPROM_BUS)
i2c_set_bus_num(old_bus);
#endif
return rcode;
}
static int tca642x_reg_read(uchar chip, uint8_t addr, uint8_t *data)
{
uint8_t valw;
int org_bus_num;
int ret = 0;
org_bus_num = i2c_get_bus_num();
i2c_set_bus_num(CONFIG_SYS_I2C_TCA642X_BUS_NUM);
if (i2c_read(chip, addr, 1, (u8 *)&valw, 1)) {
ret = -1;
goto error;
}
*data = valw;
error:
i2c_set_bus_num(org_bus_num);
return ret;
}
static void fdt_board_fixup_qe_pins(void *blob)
{
unsigned int oldbus;
u8 val8;
int node;
fsl_lbc_t *lbc = LBC_BASE_ADDR;
if (hwconfig("qe")) {
/* For QE and eLBC pins multiplexing,
* there is a PCA9555 device on P1025RDB.
* It control the multiplex pins' functions,
* and setting the PCA9555 can switch the
* function between QE and eLBC.
*/
oldbus = i2c_get_bus_num();
i2c_set_bus_num(0);
if (hwconfig("tdm"))
val8 = PCA_IOPORT_QE_TDM_ENABLE;
else
val8 = PCA_IOPORT_QE_PIN_ENABLE;
i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_CFG_CMD,
1, &val8, 1);
i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_OUTPUT_CMD,
1, &val8, 1);
i2c_set_bus_num(oldbus);
/* if run QE TDM, Set ABSWP to implement
* conversion of addresses in the eLBC.
*/
if (hwconfig("tdm")) {
set_lbc_or(2, CONFIG_PMC_OR_PRELIM);
set_lbc_br(2, CONFIG_PMC_BR_PRELIM);
setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
}
} else {
node = fdt_path_offset(blob, "/qe");
if (node >= 0)
fdt_del_node(blob, node);
}
return;
}
/*
* pib_init() -- Initialize the PCA9555 IO expander on the PIB board
*/
void
pib_init(void)
{
u8 val8, orig_i2c_bus;
/*
* Assign PIB PMC2/3 to PCI bus
*/
/*switch temporarily to I2C bus #2 */
orig_i2c_bus = i2c_get_bus_num();
i2c_set_bus_num(1);
val8 = 0x00;
i2c_write(0x23, 0x6, 1, &val8, 1);
i2c_write(0x23, 0x7, 1, &val8, 1);
val8 = 0xff;
i2c_write(0x23, 0x2, 1, &val8, 1);
i2c_write(0x23, 0x3, 1, &val8, 1);
val8 = 0x00;
i2c_write(0x26, 0x6, 1, &val8, 1);
val8 = 0x34;
i2c_write(0x26, 0x7, 1, &val8, 1);
val8 = 0xf9;
i2c_write(0x26, 0x2, 1, &val8, 1);
val8 = 0xff;
i2c_write(0x26, 0x3, 1, &val8, 1);
val8 = 0x00;
i2c_write(0x27, 0x6, 1, &val8, 1);
i2c_write(0x27, 0x7, 1, &val8, 1);
val8 = 0xff;
i2c_write(0x27, 0x2, 1, &val8, 1);
val8 = 0xef;
i2c_write(0x27, 0x3, 1, &val8, 1);
asm("eieio");
i2c_set_bus_num(orig_i2c_bus);
}
int board_init(void)
{
int i;
struct i2c_pads_info *p = i2c_pads + i2c_get_info_entry_offset();
struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
u8 orig_i2c_bus;
u8 val8;
clrsetbits_le32(&iomuxc_regs->gpr[1],
IOMUXC_GPR1_OTG_ID_MASK,
IOMUXC_GPR1_OTG_ID_GPIO1);
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
for (i = 0; i < 3; i++) {
setup_i2c(i, CONFIG_SYS_I2C_SPEED, 0x7f, p);
p += I2C_PADS_INFO_ENTRY_SPACING;
}
#ifdef CONFIG_CMD_SATA
setup_sata();
#endif
orig_i2c_bus = i2c_get_bus_num();
i2c_set_bus_num(2);
val8 = 0x7f; /* 4.0A source */
i2c_write(0x69, 0xc0, 1, &val8, 1);
val8 = 0x0c; /* Protection allow 0xb9 write */
i2c_write(0x69, 0xbd, 1, &val8, 1);
val8 = 0x14; /* 1A charge */
i2c_write(0x69, 0xb9, 1, &val8, 1);
i2c_set_bus_num(orig_i2c_bus);
#ifdef CONFIG_CMD_FBPANEL
fbp_setup_display(displays, ARRAY_SIZE(displays));
#endif
return 0;
}
int dtt_i2c(void)
{
#if defined CONFIG_DTT_SENSORS
int i;
unsigned char sensors[] = CONFIG_DTT_SENSORS;
int old_bus;
/* Force a compilation error, if there are more then 32 sensors */
BUILD_BUG_ON(sizeof(sensors) > 32);
/* switch to correct I2C bus */
#ifdef CONFIG_SYS_I2C
old_bus = i2c_get_bus_num();
i2c_set_bus_num(CONFIG_SYS_DTT_BUS_NUM);
#else
old_bus = I2C_GET_BUS();
I2C_SET_BUS(CONFIG_SYS_DTT_BUS_NUM);
#endif
_initialize_dtt();
/*
* Loop through sensors, read
* temperature, and output it.
*/
for (i = 0; i < sizeof(sensors); i++)
printf("DTT%d: %i C\n", i + 1, dtt_get_temp(sensors[i]));
/* switch back to original I2C bus */
#ifdef CONFIG_SYS_I2C
i2c_set_bus_num(old_bus);
#else
I2C_SET_BUS(old_bus);
#endif
#endif
return 0;
}
/*
* Modify masked bits in register
*/
static int tca642x_reg_write(uchar chip, uint8_t addr,
uint8_t reg_bit, uint8_t data)
{
uint8_t valw;
int org_bus_num;
int ret;
org_bus_num = i2c_get_bus_num();
i2c_set_bus_num(CONFIG_SYS_I2C_TCA642X_BUS_NUM);
if (i2c_read(chip, addr, 1, (uint8_t *)&valw, 1)) {
printf("Could not read before writing\n");
ret = -1;
goto error;
}
valw &= ~reg_bit;
valw |= data;
ret = i2c_write(chip, addr, 1, (u8 *)&valw, 1);
error:
i2c_set_bus_num(org_bus_num);
return ret;
}
static int do_date(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
struct rtc_time tm;
int rcode = 0;
int old_bus __maybe_unused;
/* switch to correct I2C bus */
#ifdef CONFIG_DM_RTC
struct udevice *dev;
rcode = uclass_get_device(UCLASS_RTC, 0, &dev);
if (rcode) {
printf("Cannot find RTC: err=%d\n", rcode);
return CMD_RET_FAILURE;
}
#elif defined(CONFIG_SYS_I2C)
old_bus = i2c_get_bus_num();
i2c_set_bus_num(CONFIG_SYS_RTC_BUS_NUM);
#else
old_bus = I2C_GET_BUS();
I2C_SET_BUS(CONFIG_SYS_RTC_BUS_NUM);
#endif
switch (argc) {
case 2: /* set date & time */
if (strcmp(argv[1],"reset") == 0) {
puts ("Reset RTC...\n");
#ifdef CONFIG_DM_RTC
rcode = dm_rtc_reset(dev);
if (!rcode)
rcode = dm_rtc_set(dev, &default_tm);
#else
rtc_reset();
rcode = rtc_set(&default_tm);
#endif
if (rcode)
puts("## Failed to set date after RTC reset\n");
} else {
/* initialize tm with current time */
#ifdef CONFIG_DM_RTC
rcode = dm_rtc_get(dev, &tm);
#else
rcode = rtc_get(&tm);
#endif
if (!rcode) {
/* insert new date & time */
if (mk_date(argv[1], &tm) != 0) {
puts ("## Bad date format\n");
break;
}
/* and write to RTC */
#ifdef CONFIG_DM_RTC
rcode = dm_rtc_set(dev, &tm);
#else
rcode = rtc_set(&tm);
#endif
if (rcode) {
printf("## Set date failed: err=%d\n",
rcode);
}
} else {
puts("## Get date failed\n");
}
}
/* FALL TROUGH */
case 1: /* get date & time */
#ifdef CONFIG_DM_RTC
rcode = dm_rtc_get(dev, &tm);
#else
rcode = rtc_get(&tm);
#endif
if (rcode) {
puts("## Get date failed\n");
break;
}
printf ("Date: %4d-%02d-%02d (%sday) Time: %2d:%02d:%02d\n",
tm.tm_year, tm.tm_mon, tm.tm_mday,
(tm.tm_wday<0 || tm.tm_wday>6) ?
"unknown " : RELOC(weekdays[tm.tm_wday]),
tm.tm_hour, tm.tm_min, tm.tm_sec);
break;
default:
rcode = CMD_RET_USAGE;
}
/* switch back to original I2C bus */
#ifdef CONFIG_SYS_I2C
i2c_set_bus_num(old_bus);
#elif !defined(CONFIG_DM_RTC)
I2C_SET_BUS(old_bus);
#endif
return rcode ? CMD_RET_FAILURE : 0;
}