_attribute_ram_code_ void irq_handler(void)
{
u8 src_rf = reg_rf_irq_status;
src = reg_irq_src;
HostCmdStatus = read_reg8(0x800021);
HostPacketStatus = read_reg8(0x800022);
irq_num++;
if (HostPacketStatus & 0x06) {
if(i2c_irq_handler)
i2c_irq_handler();
if(HostPacketStatus&0x04){
hostcmdirq_w++;
write_reg8(0x800022,0x04);
}
if(HostPacketStatus&0x02){
hostcmdirq_r++;
write_reg8(0x800022,0x02);
}
write_reg8(0x800020, 0x00);
}
if(IRQ_TIMER1_ENABLE && (src & FLD_IRQ_TMR1_EN)){
if(timer_irq1_handler)
timer_irq1_handler();
reg_irq_src = FLD_IRQ_TMR1_EN;
}
// should use FLD_IRQ_GPIO_RISC2_EN for compatibility with 86xx/85xx
if(IRQ_GPIO_ENABLE && (src & FLD_IRQ_GPIO_RISC0_EN)){
#ifndef WIN32
if(gpio_user_irq_handler)
gpio_user_irq_handler();
#endif
reg_irq_src = FLD_IRQ_GPIO_RISC0_EN;
}
#if(!APPLICATION_DONGLE)
if(IRQ_GPIO0_ENABLE && (src & FLD_IRQ_GPIO_RISC2_EN)){
#ifndef WIN32
if(gpio0_user_irq_handler)
gpio0_user_irq_handler();
#endif
reg_irq_src = FLD_IRQ_GPIO_RISC2_EN;
}
#endif
if((src_rf & FLD_RF_IRQ_RX)){
if(rf_rx_irq_handler)
rf_rx_irq_handler();
reg_rf_irq_status = FLD_RF_IRQ_RX;
}
if((src_rf & FLD_RF_IRQ_TX)){
if(rf_tx_irq_handler)
rf_tx_irq_handler();
reg_rf_irq_status = FLD_RF_IRQ_TX;
}
}
void __irq_i2c2_ev(void) {
i2c_irq_handler(&i2c_dev2);
}
void __irq_i2c1_ev(void) {
i2c_irq_handler(&i2c_dev1);
}
/*
* i2c_read_msg
* return: 0 success
* -1 fail
*/
static int i2c_read_msg(unsigned short slave_addr,
unsigned char *buf,
unsigned short length,
int restart,
int last)
{
unsigned short tcr_value ;
unsigned int xfer_length ;
unsigned int timeout ;
if (length == 0)
return -1 ;
xfer_length = 0 ;
i2c.isr_nack = 0 ;
i2c.isr_byte_end = 0 ;
i2c.isr_timeout = 0 ;
if (i2c.i2c_mode == I2C_STANDARD_MODE)
tcr_value = (unsigned short)(I2C_TCR_STANDARD_MODE|I2C_TCR_MASTER_READ |\
(slave_addr & I2C_TCR_SLAVE_ADDR_MASK)) ;
else if (i2c.i2c_mode == I2C_FAST_MODE)
tcr_value = (unsigned short)(I2C_TCR_FAST_MODE|I2C_TCR_MASTER_READ |\
(slave_addr & I2C_TCR_SLAVE_ADDR_MASK)) ;
else
tcr_value = (unsigned short)(I2C_TCR_HS_MODE|I2C_TCR_MASTER_READ |\
(slave_addr & I2C_TCR_SLAVE_ADDR_MASK)) ;
i2c.regs->IICTCR = tcr_value;
/*repeat start case*/
if (restart == 1)
i2c.regs->IICCR |= I2C_CR_CPU_RDY ;
if (length == 1)
i2c.regs->IICCR |= I2C_CR_TX_NEXT_NO_ACK; /*only 8-bit to read*/
while (1) {
timeout = 500000 ;
while (1) {
i2c_irq_handler();
if ((i2c.isr_nack == 1) || (i2c.isr_byte_end == 1) || (i2c.isr_timeout == 1))
break ;
--timeout ;
if (timeout == 0)
break ;
}
/* fail case*/
if (i2c.isr_nack == 1) {
PRINTD("i2c_err : write NACK error (rx) \n\r") ;
return -1 ;
}
if (i2c.isr_timeout == 1) {
PRINTD("%s, i2c_err : write SCL timeout error (rx)\n\r", __func__) ;
return -1 ;
}
if (timeout == 0) {
PRINTD("[%s]i2c_err: write software timeout error (rx) \n\r", __func__) ;
return -1 ;
}
/* pass case*/
if (i2c.isr_byte_end == 1) {
buf[xfer_length] = (i2c.regs->IICDR >> 8) ;
++xfer_length ;
}
i2c.isr_nack = 0 ;
i2c.isr_byte_end = 0 ;
i2c.isr_timeout = 0 ;
if (length > xfer_length) {
if ((length - 1) == xfer_length) /* next read is the last one*/
i2c.regs->IICCR |= (I2C_CR_TX_NEXT_NO_ACK | I2C_CR_CPU_RDY);
else
i2c.regs->IICCR |= I2C_CR_CPU_RDY ;
} else if (length == xfer_length) { /* end rx xfer*/
if (last == 1) /* stop case*/
break ;
else /* restart case*/
/* ??? how to handle the restart after read ?*/
break ;
} else {
PRINTD("i2c_err : read known error\n\r") ;
return -1 ;
}
}
/*
* i2c_write_msg
* return: 0 success
* -1 fail
*/
static int i2c_write_msg(unsigned short slave_addr,
unsigned char *buf,
unsigned short length,
int restart,
int last)
{
unsigned short tcr_value ;
unsigned int xfer_length ;
unsigned int timeout ;
if (length == 0)
return -1 ;
xfer_length = 0 ; /* for array index and also for checking counting*/
i2c.isr_nack = 0 ;
i2c.isr_byte_end = 0 ;
i2c.isr_timeout = 0 ;
i2c.regs->IICDR = (unsigned short)(buf[xfer_length] & I2C_CDR_DATA_WRITE_MASK) ;
if (i2c.i2c_mode == I2C_STANDARD_MODE)
tcr_value = (unsigned short)(I2C_TCR_STANDARD_MODE|I2C_TCR_MASTER_WRITE |\
(slave_addr & I2C_TCR_SLAVE_ADDR_MASK)) ;
else if (i2c.i2c_mode == I2C_FAST_MODE)
tcr_value = (unsigned short)(I2C_TCR_FAST_MODE|I2C_TCR_MASTER_WRITE |\
(slave_addr & I2C_TCR_SLAVE_ADDR_MASK)) ;
else {
tcr_value = (unsigned short)(I2C_TCR_HS_MODE|I2C_TCR_MASTER_WRITE |\
(slave_addr & I2C_TCR_SLAVE_ADDR_MASK)) ;
i2c.regs->IICDIV = HS_MASTER_CODE;
}
/* SET TRANSFER MODE*/
i2c.regs->IICTCR = tcr_value ;
/*repeat start case*/
if (restart == 1)
i2c.regs->IICCR |= I2C_CR_CPU_RDY ;
while (1) {
timeout = 500000 ;
while (1) {
i2c_irq_handler();
if ((i2c.isr_nack == 1) || (i2c.isr_byte_end == 1) || (i2c.isr_timeout == 1))
break ;
--timeout ;
if (timeout == 0)
break ;
}
/* fail case*/
if (timeout == 0) {
PRINTD("[%s]i2c_err : wrire software timeout error (tx)\n\r", __func__) ;
return -1 ;
}
if (i2c.isr_nack == 1) {
PRINTD("i2c_err : write NACK error (tx) \n\r") ;
return -1 ;
}
if (i2c.isr_timeout == 1) {
PRINTD("%s:i2c_err : write SCL timeout error (tx)\n\r", __func__) ;
return -1 ;
}
/* pass case*/
if (i2c.isr_byte_end == 1)
++xfer_length ;
i2c.isr_nack = 0 ;
i2c.isr_byte_end = 0 ;
i2c.isr_timeout = 0 ;
if ((i2c.regs->IICSR & I2C_CSR_RCV_ACK_MASK) == I2C_CSR_RCV_NOT_ACK) {
PRINTD("i2c_err : write RCV NACK error\n\r") ;
return -1 ;
}
if (length > xfer_length) {
i2c.regs->IICDR = (unsigned short) (buf[xfer_length] & I2C_CDR_DATA_WRITE_MASK) ;
i2c.regs->IICCR = (I2C_CR_CPU_RDY | I2C_CR_ENABLE) ;
} else if (length == xfer_length) { /* end tx xfer*/
if (last == 1) { /* stop case*/
//i2c.regs->IICCR = (I2C_CR_TX_END|I2C_CR_CPU_RDY|I2C_CR_ENABLE) ;
wmt_delayus(2);/*2 us*/
i2c.regs->IICCR |= (I2C_CR_TX_END) ;
break ;
} else { /* restart case*/
/* handle the restart for first write then the next is read*/
i2c.regs->IICCR = (I2C_CR_ENABLE) ;
break ;
}
} else {
PRINTD("i2c_err : write unknown error\n\r") ;
return -1 ;
}
}
i2c.regs->IICCR &= ~(I2C_CR_TX_END|I2C_CR_CPU_RDY) ;
return 0 ;
}
