/** Initialize a new ddf driver instance of i8042 driver
*
* @param[in] device DDF instance of the device to initialize.
*
* @return Error code.
*
*/
static int i8042_dev_add(ddf_dev_t *device)
{
if (!device)
return EINVAL;
uintptr_t io_regs = 0;
size_t io_size = 0;
int kbd = 0;
int mouse = 0;
int ret = get_my_registers(device, &io_regs, &io_size, &kbd, &mouse);
CHECK_RET_RETURN(ret, "Failed to get registers: %s.",
str_error(ret));
ddf_msg(LVL_DEBUG, "I/O regs at %p (size %zuB), IRQ kbd %d, IRQ mouse %d.",
(void *) io_regs, io_size, kbd, mouse);
i8042_t *i8042 = ddf_dev_data_alloc(device, sizeof(i8042_t));
ret = (i8042 == NULL) ? ENOMEM : EOK;
CHECK_RET_RETURN(ret, "Failed to allocate i8042 driver instance.");
ret = i8042_init(i8042, (void *) io_regs, io_size, kbd, mouse, device);
CHECK_RET_RETURN(ret, "Failed to initialize i8042 driver: %s.",
str_error(ret));
ddf_msg(LVL_NOTE, "Controlling '%s' (%" PRIun ").",
ddf_dev_get_name(device), ddf_dev_get_handle(device));
return EOK;
}
void arch_post_smp_init(void)
{
/* Currently the only supported platform for ia32 is 'pc'. */
static const char *platform = "pc";
sysinfo_set_item_data("platform", NULL, (void *) platform,
str_size(platform));
#ifdef CONFIG_PC_KBD
/*
* Initialize the i8042 controller. Then initialize the keyboard
* module and connect it to i8042. Enable keyboard interrupts.
*/
i8042_instance_t *i8042_instance = i8042_init((i8042_t *) I8042_BASE, IRQ_KBD);
if (i8042_instance) {
kbrd_instance_t *kbrd_instance = kbrd_init();
if (kbrd_instance) {
indev_t *sink = stdin_wire();
indev_t *kbrd = kbrd_wire(kbrd_instance, sink);
i8042_wire(i8042_instance, kbrd);
trap_virtual_enable_irqs(1 << IRQ_KBD);
trap_virtual_enable_irqs(1 << IRQ_MOUSE);
}
}
#endif
if (irqs_info != NULL)
sysinfo_set_item_val(irqs_info, NULL, true);
}
/** PC platform initialization. */
__init_text void platform_init(void) {
pic_init();
acpi_init();
/* If the LAPIC is not available, we must use the PIT as the timer. */
if(!lapic_enabled())
pit_init();
i8042_init();
}
void arch_init() {
i8042_init();
if (apic_is_available()) {
apic_init();
} else {
// pic_init();
// pit_init();
}
}
static
void mips_r4k_init (ram_addr_t ram_size, int vga_ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
char buf[1024];
unsigned long bios_offset;
int bios_size;
CPUState *env;
RTCState *rtc_state;
int i;
qemu_irq *i8259;
int index;
BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
/* init CPUs */
if (cpu_model == NULL) {
#ifdef TARGET_MIPS64
cpu_model = "R4000";
#else
cpu_model = "24Kf";
#endif
}
env = cpu_init(cpu_model);
if (!env) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
qemu_register_reset(main_cpu_reset, env);
/* allocate RAM */
if (ram_size > (256 << 20)) {
fprintf(stderr,
"qemu: Too much memory for this machine: %d MB, maximum 256 MB\n",
((unsigned int)ram_size / (1 << 20)));
exit(1);
}
cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
if (!mips_qemu_iomemtype) {
mips_qemu_iomemtype = cpu_register_io_memory(0, mips_qemu_read,
mips_qemu_write, NULL);
}
cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype);
/* Try to load a BIOS image. If this fails, we continue regardless,
but initialize the hardware ourselves. When a kernel gets
preloaded we also initialize the hardware, since the BIOS wasn't
run. */
bios_offset = ram_size + vga_ram_size;
if (bios_name == NULL)
bios_name = BIOS_FILENAME;
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
bios_size = load_image(buf, phys_ram_base + bios_offset);
if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) {
cpu_register_physical_memory(0x1fc00000,
BIOS_SIZE, bios_offset | IO_MEM_ROM);
} else if ((index = drive_get_index(IF_PFLASH, 0, 0)) > -1) {
uint32_t mips_rom = 0x00400000;
cpu_register_physical_memory(0x1fc00000, mips_rom,
qemu_ram_alloc(mips_rom) | IO_MEM_ROM);
if (!pflash_cfi01_register(0x1fc00000, qemu_ram_alloc(mips_rom),
drives_table[index].bdrv, sector_len, mips_rom / sector_len,
4, 0, 0, 0, 0)) {
fprintf(stderr, "qemu: Error registering flash memory.\n");
}
}
else {
/* not fatal */
fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
buf);
}
if (kernel_filename) {
loaderparams.ram_size = ram_size;
loaderparams.kernel_filename = kernel_filename;
loaderparams.kernel_cmdline = kernel_cmdline;
loaderparams.initrd_filename = initrd_filename;
load_kernel (env);
}
/* Init CPU internal devices */
cpu_mips_irq_init_cpu(env);
cpu_mips_clock_init(env);
/* The PIC is attached to the MIPS CPU INT0 pin */
i8259 = i8259_init(env->irq[2]);
rtc_state = rtc_init(0x70, i8259[8], 2000);
/* Register 64 KB of ISA IO space at 0x14000000 */
isa_mmio_init(0x14000000, 0x00010000);
isa_mem_base = 0x10000000;
pit = pit_init(0x40, i8259[0]);
for(i = 0; i < MAX_SERIAL_PORTS; i++) {
if (serial_hds[i]) {
serial_init(serial_io[i], i8259[serial_irq[i]], 115200,
serial_hds[i]);
}
}
isa_vga_init(phys_ram_base + ram_size, ram_size,
vga_ram_size);
if (nd_table[0].vlan)
isa_ne2000_init(0x300, i8259[9], &nd_table[0]);
if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
fprintf(stderr, "qemu: too many IDE bus\n");
exit(1);
}
for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
if (index != -1)
hd[i] = drives_table[index].bdrv;
else
hd[i] = NULL;
}
for(i = 0; i < MAX_IDE_BUS; i++)
isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
hd[MAX_IDE_DEVS * i],
hd[MAX_IDE_DEVS * i + 1]);
i8042_init(i8259[1], i8259[12], 0x60);
}
static void sun4uv_init(ram_addr_t RAM_size, int vga_ram_size,
const char *boot_devices,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model,
const struct hwdef *hwdef)
{
CPUState *env;
char buf[1024];
m48t59_t *nvram;
int ret, linux_boot;
unsigned int i;
ram_addr_t ram_offset, prom_offset, vga_ram_offset;
long initrd_size, kernel_size;
PCIBus *pci_bus, *pci_bus2, *pci_bus3;
QEMUBH *bh;
qemu_irq *irq;
int drive_index;
BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
BlockDriverState *fd[MAX_FD];
void *fw_cfg;
ResetData *reset_info;
linux_boot = (kernel_filename != NULL);
/* init CPUs */
if (!cpu_model)
cpu_model = hwdef->default_cpu_model;
env = cpu_init(cpu_model);
if (!env) {
fprintf(stderr, "Unable to find Sparc CPU definition\n");
exit(1);
}
bh = qemu_bh_new(tick_irq, env);
env->tick = ptimer_init(bh);
ptimer_set_period(env->tick, 1ULL);
bh = qemu_bh_new(stick_irq, env);
env->stick = ptimer_init(bh);
ptimer_set_period(env->stick, 1ULL);
bh = qemu_bh_new(hstick_irq, env);
env->hstick = ptimer_init(bh);
ptimer_set_period(env->hstick, 1ULL);
reset_info = qemu_mallocz(sizeof(ResetData));
reset_info->env = env;
reset_info->reset_addr = hwdef->prom_addr + 0x40ULL;
qemu_register_reset(main_cpu_reset, reset_info);
main_cpu_reset(reset_info);
// Override warm reset address with cold start address
env->pc = hwdef->prom_addr + 0x20ULL;
env->npc = env->pc + 4;
/* allocate RAM */
ram_offset = qemu_ram_alloc(RAM_size);
cpu_register_physical_memory(0, RAM_size, ram_offset);
prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
cpu_register_physical_memory(hwdef->prom_addr,
(PROM_SIZE_MAX + TARGET_PAGE_SIZE) &
TARGET_PAGE_MASK,
prom_offset | IO_MEM_ROM);
if (bios_name == NULL)
bios_name = PROM_FILENAME;
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
ret = load_elf(buf, hwdef->prom_addr - PROM_VADDR, NULL, NULL, NULL);
if (ret < 0) {
ret = load_image_targphys(buf, hwdef->prom_addr,
(PROM_SIZE_MAX + TARGET_PAGE_SIZE) &
TARGET_PAGE_MASK);
if (ret < 0) {
fprintf(stderr, "qemu: could not load prom '%s'\n",
buf);
exit(1);
}
}
kernel_size = 0;
initrd_size = 0;
if (linux_boot) {
/* XXX: put correct offset */
kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
if (kernel_size < 0)
kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
ram_size - KERNEL_LOAD_ADDR);
if (kernel_size < 0)
kernel_size = load_image_targphys(kernel_filename,
KERNEL_LOAD_ADDR,
ram_size - KERNEL_LOAD_ADDR);
if (kernel_size < 0) {
fprintf(stderr, "qemu: could not load kernel '%s'\n",
kernel_filename);
exit(1);
}
/* load initrd */
if (initrd_filename) {
initrd_size = load_image_targphys(initrd_filename,
INITRD_LOAD_ADDR,
ram_size - INITRD_LOAD_ADDR);
if (initrd_size < 0) {
fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
initrd_filename);
exit(1);
}
}
if (initrd_size > 0) {
for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
break;
}
}
}
}
pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL, &pci_bus2,
&pci_bus3);
isa_mem_base = VGA_BASE;
vga_ram_offset = qemu_ram_alloc(vga_ram_size);
pci_vga_init(pci_bus, phys_ram_base + vga_ram_offset,
vga_ram_offset, vga_ram_size,
0, 0);
// XXX Should be pci_bus3
pci_ebus_init(pci_bus, -1);
i = 0;
if (hwdef->console_serial_base) {
serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200,
serial_hds[i], 1);
i++;
}
for(; i < MAX_SERIAL_PORTS; i++) {
if (serial_hds[i]) {
serial_init(serial_io[i], NULL/*serial_irq[i]*/, 115200,
serial_hds[i]);
}
}
for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
if (parallel_hds[i]) {
parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/,
parallel_hds[i]);
}
}
for(i = 0; i < nb_nics; i++)
pci_nic_init(pci_bus, &nd_table[i], -1, "ne2k_pci");
irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
fprintf(stderr, "qemu: too many IDE bus\n");
exit(1);
}
for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
drive_index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS,
i % MAX_IDE_DEVS);
if (drive_index != -1)
hd[i] = drives_table[drive_index].bdrv;
else
hd[i] = NULL;
}
pci_cmd646_ide_init(pci_bus, hd, 1);
/* FIXME: wire up interrupts. */
i8042_init(NULL/*1*/, NULL/*12*/, 0x60);
for(i = 0; i < MAX_FD; i++) {
drive_index = drive_get_index(IF_FLOPPY, 0, i);
if (drive_index != -1)
fd[i] = drives_table[drive_index].bdrv;
else
fd[i] = NULL;
}
floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd);
nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59);
sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
KERNEL_LOAD_ADDR, kernel_size,
kernel_cmdline,
INITRD_LOAD_ADDR, initrd_size,
/* XXX: need an option to load a NVRAM image */
0,
graphic_width, graphic_height, graphic_depth,
(uint8_t *)&nd_table[0].macaddr);
fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
}
