void gendiv()
{
#ifdef INTERPRET_DIV
gencallinterp((unsigned long)DIV, 0);
#else
int rs, rt;
allocate_register_manually_w(EAX, (unsigned long *)&lo, 0);
allocate_register_manually_w(EDX, (unsigned long *)&hi, 0);
rs = allocate_register((unsigned long*)dst->f.r.rs);
rt = allocate_register((unsigned long*)dst->f.r.rt);
cmp_reg32_imm32(rt, 0);
je_rj((rs == EAX ? 0 : 2) + 1 + 2);
mov_reg32_reg32(EAX, rs); // 0 or 2
cdq(); // 1
idiv_reg32(rt); // 2
#endif
}
void gendiv(usf_state_t * state)
{
#ifdef INTERPRET_DIV
gencallinterp(state, (unsigned int)state->current_instruction_table.DIV, 0);
#else
int rs, rt;
allocate_register_manually_w(state, EAX, (unsigned int *)&state->lo, 0);
allocate_register_manually_w(state, EDX, (unsigned int *)&state->hi, 0);
rs = allocate_register(state, (unsigned int*)state->dst->f.r.rs);
rt = allocate_register(state, (unsigned int*)state->dst->f.r.rt);
cmp_reg32_imm32(state, rt, 0);
je_rj(state, (rs == EAX ? 0 : 2) + 1 + 2);
mov_reg32_reg32(state, EAX, rs); // 0 or 2
cdq(state); // 1
idiv_reg32(state, rt); // 2
#endif
}
void gendiv(void)
{
#ifdef INTERPRET_DIV
gencallinterp((unsigned int)cached_interpreter_table.DIV, 0);
#else
int rs, rt;
allocate_register_manually_w(EAX, (unsigned int *)r4300_mult_lo(), 0);
allocate_register_manually_w(EDX, (unsigned int *)r4300_mult_hi(), 0);
rs = allocate_register((unsigned int*)g_dev.r4300.recomp.dst->f.r.rs);
rt = allocate_register((unsigned int*)g_dev.r4300.recomp.dst->f.r.rt);
cmp_reg32_imm32(rt, 0);
je_rj((rs == EAX ? 0 : 2) + 1 + 2);
mov_reg32_reg32(EAX, rs); // 0 or 2
cdq(); // 1
idiv_reg32(rt); // 2
#endif
}
void gendiv(void)
{
#if defined(COUNT_INSTR)
inc_m32abs(&instr_count[73]);
#endif
#ifdef INTERPRET_DIV
gencallinterp((unsigned long long)DIV, 0);
#else
int rs, rt;
allocate_register_32_manually_w(EAX, (unsigned int *)&lo);
allocate_register_32_manually_w(EDX, (unsigned int *)&hi);
rs = allocate_register_32((unsigned int*)dst->f.r.rs);
rt = allocate_register_32((unsigned int*)dst->f.r.rt);
cmp_reg32_imm32(rt, 0);
je_rj((rs == EAX ? 0 : 2) + 1 + 2);
mov_reg32_reg32(EAX, rs); // 0 or 2
cdq(); // 1
idiv_reg32(rt); // 2
#endif
}