__s32 BSP_disp_lcd_open_before(__u32 sel) { disp_clk_cfg(sel, DISP_OUTPUT_TYPE_LCD, DIS_NULL); lcdc_clk_on(sel); image_clk_on(sel); /* * set image normal channel start bit, because every de_clk_off( ) * will reset this bit */ Image_open(sel); Disp_lcdc_pin_cfg(sel, DISP_OUTPUT_TYPE_LCD, 1); if (gpanel_info[sel].tcon_index == 0) TCON0_cfg(sel, (__panel_para_t *) &gpanel_info[sel]); else TCON1_cfg_ex(sel, (__panel_para_t *) &gpanel_info[sel]); #ifdef CONFIG_ARCH_SUN4I BSP_disp_set_output_csc(sel, DISP_OUTPUT_TYPE_LCD); #else BSP_disp_set_output_csc(sel, DISP_OUTPUT_TYPE_LCD, gdisp.screen[sel].iep_status & DRC_USED); #endif DE_BE_set_display_size(sel, gpanel_info[sel].lcd_x, gpanel_info[sel].lcd_y); DE_BE_Output_Select(sel, sel); open_flow[sel].func_num = 0; lcd_panel_fun[sel].cfg_open_flow(sel); return DIS_SUCCESS; }
__s32 BSP_disp_hdmi_open(__u32 sel) { if(!(gdisp.screen[sel].status & HDMI_ON)) { __disp_tv_mode_t tv_mod; __u32 scaler_index; tv_mod = gdisp.screen[sel].hdmi_mode; hdmi_clk_on(); lcdc_clk_on(sel); image_clk_on(sel); Image_open(sel);//set image normal channel start bit , because every de_clk_off( )will reset this bit disp_clk_cfg(sel,DISP_OUTPUT_TYPE_HDMI, tv_mod); BSP_disp_set_output_csc(sel, DISP_OUTPUT_TYPE_HDMI); DE_BE_set_display_size(sel, tv_mode_to_width(tv_mod), tv_mode_to_height(tv_mod)); DE_BE_Output_Select(sel, sel); DE_BE_Set_Outitl_enable(sel, Disp_get_screen_scan_mode(tv_mod)); for(scaler_index=0; scaler_index<2; scaler_index++) { if((gdisp.scaler[scaler_index].status & SCALER_USED) && (gdisp.scaler[scaler_index].screen_index == sel)) { if(Disp_get_screen_scan_mode(tv_mod) == 1)//interlace output { Scaler_Set_Outitl(scaler_index, TRUE); } else { Scaler_Set_Outitl(scaler_index, FALSE); } } } TCON1_set_hdmi_mode(sel,tv_mod); TCON1_open(sel); if(gdisp.init_para.Hdmi_open) { gdisp.init_para.Hdmi_open(); } else { DE_WRN("Hdmi_open is NULL\n"); return -1; } Disp_Switch_Dram_Mode(DISP_OUTPUT_TYPE_HDMI, tv_mod); gdisp.screen[sel].b_out_interlace = Disp_get_screen_scan_mode(tv_mod); gdisp.screen[sel].status |= HDMI_ON; gdisp.screen[sel].lcdc_status |= LCDC_TCON1_USED; gdisp.screen[sel].output_type = DISP_OUTPUT_TYPE_HDMI; #ifdef __LINUX_OSAL__ Display_set_fb_timming(sel); #endif } return DIS_SUCCESS; }
__s32 BSP_disp_tv_open(__u32 sel) { if(!(gdisp.screen[sel].status & TV_ON)) { __disp_tv_mode_t tv_mod; tv_mod = gdisp.screen[sel].tv_mode; image_clk_on(sel); Image_open(sel);//set image normal channel start bit , because every de_clk_off( )will reset this bit disp_clk_cfg(sel,DISP_OUTPUT_TYPE_TV, tv_mod); tve_clk_on(); lcdc_clk_on(sel); TCON1_set_tv_mode(sel,tv_mod); TVE_set_tv_mode(sel, tv_mod); Disp_TVEC_DacCfg(sel, tv_mod); TCON1_open(sel); Disp_TVEC_Open(sel); Disp_Switch_Dram_Mode(DISP_OUTPUT_TYPE_TV, tv_mod); gdisp.screen[sel].status |= TV_ON; gdisp.screen[sel].lcdc_status |= LCDC_TCON1_USED; gdisp.screen[sel].output_type = DISP_OUTPUT_TYPE_TV; } return DIS_SUCCESS; }
__s32 Image_init(__u32 sel) { image_clk_init(sel); image_clk_on(sel); //when access image registers, must open MODULE CLOCK of image DE_BE_Reg_Init(sel); if(sel == 0) { BSP_disp_sprite_init(sel); } //DE_BE_Ready_Enable(sel, TRUE); Image_open(sel); if(sel == 0) { DE_BE_EnableINT(sel, DE_IMG_IRDY_IE); }//DE_BE_EnableINT(sel , DE_IMG_IRDY_IE); //when sel == 1, can't process when image0 module clk close //image_clk_off(sel); //close MODULE CLOCK of image if(sel == 0) { OSAL_RegISR(INTC_IRQNO_IMAGE0,0,Image_event_proc, (void *)sel,0,0); //OSAL_InterruptEnable(INTC_IRQNO_IMAGE0); } else if(sel == 1) { OSAL_RegISR(INTC_IRQNO_IMAGE1,0,Image_event_proc, (void *)sel,0,0); //OSAL_InterruptEnable(INTC_IRQNO_IMAGE1); } return DIS_SUCCESS; }
__s32 BSP_disp_lcd_open_before(__u32 sel) { disp_clk_cfg(sel, DISP_OUTPUT_TYPE_LCD, DIS_NULL); lcdc_clk_on(sel); image_clk_on(sel); Image_open(sel);//set image normal channel start bit , because every de_clk_off( )will reset this bit Disp_lcdc_pin_cfg(sel, DISP_OUTPUT_TYPE_LCD, 1); if(gpanel_info[sel].tcon_index == 0) { TCON0_cfg(sel,(__panel_para_t*)&gpanel_info[sel]); } else { TCON1_cfg_ex(sel,(__panel_para_t*)&gpanel_info[sel]); } BSP_disp_set_output_csc(sel, DISP_OUTPUT_TYPE_LCD); DE_BE_set_display_size(sel, gpanel_info[sel].lcd_x, gpanel_info[sel].lcd_y); DE_BE_Output_Select(sel, sel); open_flow[sel].func_num = 0; lcd_panel_fun[sel].cfg_open_flow(sel); return DIS_SUCCESS; }
__s32 Image_init(__u32 screen_id) { image_clk_init(screen_id); /* when access image registers, must open MODULE CLOCK of image */ image_clk_on(screen_id, 0); DE_BE_Reg_Init(screen_id); Image_open(screen_id); DE_BE_EnableINT(screen_id, DE_IMG_REG_LOAD_FINISH); DE_BE_reg_auto_load_en(screen_id, 0); if(screen_id == 0) { OSAL_RegISR(gdisp.init_para.irq[DISP_MOD_BE0],0,scaler_event_proc, (void *)screen_id,0,0); #ifndef __LINUX_OSAL__ OSAL_InterruptEnable(gdisp.init_para.irq[DISP_MOD_BE0]); #endif } else if(screen_id == 1) { OSAL_RegISR(gdisp.init_para.irq[DISP_MOD_BE1],0,scaler_event_proc, (void *)screen_id,0,0); #ifndef __LINUX_OSAL__ OSAL_InterruptEnable(gdisp.init_para.irq[DISP_MOD_BE1]); #endif } return DIS_SUCCESS; }
__s32 BSP_disp_tv_open(__u32 sel) { if((!(gdisp.screen[sel].status & TV_ON))) { __disp_tv_mode_t tv_mod; __panel_para_t para; memset(¶, 0, sizeof(__panel_para_t)); tv_mod = gdisp.screen[sel].tv_mode; lcdc_clk_on(sel, 0, 0); disp_clk_cfg(sel, DISP_OUTPUT_TYPE_TV, tv_mod); lcdc_clk_on(sel, 0, 1); drc_clk_open(sel,0); tcon_init(sel); image_clk_on(sel, 1); Image_open(sel);//set image normal channel start bit , because every de_clk_off( )will reset this bit BSP_disp_set_output_csc(sel, DISP_OUT_CSC_TYPE_LCD, BSP_disp_drc_get_input_csc(sel)); //LCD -->GM7121, rgb fmt DE_BE_set_display_size(sel, tv_mode_to_width(tv_mod), tv_mode_to_height(tv_mod)); DE_BE_Output_Select(sel, sel); disp_tv_get_timing(¶, tv_mod); tcon0_cfg(sel,(__panel_para_t*)¶); tcon0_src_select(sel,4); if(gdisp.screen[sel].tv_ops.tv_power_on) { gdisp.screen[sel].tv_ops.tv_power_on(1); msleep(500); } disp_tv_pin_cfg(1); tcon0_open(sel,(__panel_para_t*)¶); if(gdisp.screen[sel].tv_ops.tv_open) { gdisp.screen[sel].tv_ops.tv_open(); } Disp_Switch_Dram_Mode(DISP_OUTPUT_TYPE_TV, tv_mod); gdisp.screen[sel].b_out_interlace = Disp_get_screen_scan_mode(tv_mod); gdisp.screen[sel].status = TV_ON; gdisp.screen[sel].lcdc_status |= LCDC_TCON0_USED; gdisp.screen[sel].output_type = DISP_OUTPUT_TYPE_TV; gdisp.screen[sel].output_csc_type = DISP_OUT_CSC_TYPE_LCD;//LCD -->GM7121, rgb fmt if(BSP_disp_cmu_get_enable(sel) ==1) { IEP_CMU_Set_Imgsize(sel, BSP_disp_get_screen_width(sel), BSP_disp_get_screen_height(sel)); } Disp_set_out_interlace(sel); #ifdef __LINUX_OSAL__ Display_set_fb_timming(sel); #endif tcon0_src_select(sel,0); } return DIS_SUCCESS; }
__s32 BSP_disp_vga_open(__u32 sel) { if (!(gdisp.screen[sel].status & VGA_ON)) { __disp_vga_mode_t vga_mode; __u32 i = 0; vga_mode = gdisp.screen[sel].vga_mode; lcdc_clk_on(sel); image_clk_on(sel); /* * set image normal channel start bit , because every * de_clk_off( ) will reset this bit */ Image_open(sel); tve_clk_on(sel); disp_clk_cfg(sel, DISP_OUTPUT_TYPE_VGA, vga_mode); Disp_lcdc_pin_cfg(sel, DISP_OUTPUT_TYPE_VGA, 1); #ifdef CONFIG_ARCH_SUN4I BSP_disp_set_output_csc(sel, DISP_OUTPUT_TYPE_VGA); #else BSP_disp_set_output_csc(sel, DISP_OUTPUT_TYPE_VGA, gdisp.screen[sel]. iep_status & DRC_USED); #endif DE_BE_set_display_size(sel, vga_mode_to_width(vga_mode), vga_mode_to_height(vga_mode)); DE_BE_Output_Select(sel, sel); TCON1_set_vga_mode(sel, vga_mode); TVE_set_vga_mode(sel); Disp_TVEC_Open(sel); TCON1_open(sel); for (i = 0; i < 4; i++) { if (gdisp.screen[sel].dac_source[i] == DISP_TV_DAC_SRC_COMPOSITE) { TVE_dac_set_source(1 - sel, i, DISP_TV_DAC_SRC_COMPOSITE); TVE_dac_sel(1 - sel, i, i); } } Disp_Switch_Dram_Mode(DISP_OUTPUT_TYPE_VGA, vga_mode); gdisp.screen[sel].b_out_interlace = 0; gdisp.screen[sel].status |= VGA_ON; gdisp.screen[sel].lcdc_status |= LCDC_TCON1_USED; gdisp.screen[sel].output_type = DISP_OUTPUT_TYPE_VGA; Display_set_fb_timing(sel); } return DIS_SUCCESS; }
__s32 Image_init(__u32 sel) { image_clk_init(sel); image_clk_on(sel, 0); //when access image registers, must open MODULE CLOCK of image DE_BE_Reg_Init(sel); BSP_disp_sprite_init(sel); DE_BE_reg_auto_load_en(sel, 0); DE_BE_DisableINT(sel, DE_IMG_REG_LOAD_FINISH); image_clk_off(sel, 0); return DIS_SUCCESS; }
__s32 bsp_disp_vga_open(__u32 screen_id) { if(!(gdisp.screen[screen_id].status & VGA_ON)) { __disp_vga_mode_t vga_mode; __u32 i = 0; vga_mode = gdisp.screen[screen_id].vga_mode; lcdc_clk_on(screen_id, 1, 0); lcdc_clk_on(screen_id, 1, 1); tcon_init(screen_id); image_clk_on(screen_id, 1); Image_open(screen_id);//set image normal channel start bit , because every de_clk_off( )will reset this bit tve_clk_on(screen_id); disp_clk_cfg(screen_id,DISP_OUTPUT_TYPE_VGA, vga_mode); gdisp.screen[screen_id].output_csc_type = DISP_OUT_CSC_TYPE_VGA; bsp_disp_set_output_csc(screen_id, gdisp.screen[screen_id].output_csc_type, bsp_disp_drc_get_input_csc(screen_id)); DE_BE_set_display_size(screen_id, vga_mode_to_width(vga_mode), vga_mode_to_height(vga_mode)); DE_BE_Output_Select(screen_id, screen_id); tcon1_set_vga_mode(screen_id,vga_mode); TVE_set_vga_mode(screen_id); Disp_TVEC_Open(screen_id); tcon1_open(screen_id); for(i=0; i<4; i++) { if(gdisp.screen[screen_id].dac_source[i] == DISP_TV_DAC_SRC_COMPOSITE) { TVE_dac_set_source(1-screen_id, i, DISP_TV_DAC_SRC_COMPOSITE); TVE_dac_sel(1-screen_id, i, i); } } Disp_Switch_Dram_Mode(DISP_OUTPUT_TYPE_VGA, vga_mode); gdisp.screen[screen_id].b_out_interlace = 0; gdisp.screen[screen_id].status |= VGA_ON; gdisp.screen[screen_id].lcdc_status |= LCDC_TCON1_USED; gdisp.screen[screen_id].output_type = DISP_OUTPUT_TYPE_VGA; #ifdef __LINUX_OSAL__ Display_set_fb_timming(screen_id); #endif } return DIS_SUCCESS; }
__s32 Image_init(__u32 sel) { image_clk_init(sel); image_clk_on(sel); //when access image registers, must open MODULE CLOCK of image DE_BE_Reg_Init(sel); BSP_disp_sprite_init(sel); BSP_disp_set_output_csc(sel, DISP_OUTPUT_TYPE_LCD); Image_open(sel); DE_BE_EnableINT(sel, DE_IMG_REG_LOAD_FINISH); DE_BE_reg_auto_load_en(sel, 0); return DIS_SUCCESS; }
__s32 BSP_disp_lcd_open_before(__u32 sel) { disp_clk_cfg(sel, DISP_OUTPUT_TYPE_LCD, 0); lcdc_clk_on(sel); image_clk_on(sel); Image_open(sel);//set image normal channel start bit , because every de_clk_off( )will reset this bit Disp_lcdc_pin_cfg(sel, DISP_OUTPUT_TYPE_LCD, 1); if(gpanel_info[sel].tcon_index == 0) { TCON0_cfg(sel,(__ebios_panel_para_t*)&gpanel_info[sel]); } else { TCON1_cfg_ex(sel,(__ebios_panel_para_t*)&gpanel_info[sel]); } open_flow[sel].func_num = 0; lcd_panel_fun[sel].cfg_open_flow(sel); return DIS_SUCCESS; }
__s32 Image_init(__u32 sel) { image_clk_init(sel); /* when access image registers, must open MODULE CLOCK of image */ image_clk_on(sel); DE_BE_Reg_Init(sel); BSP_disp_sprite_init(sel); if (sunxi_is_sun5i()) BSP_disp_set_output_csc(sel, DISP_OUTPUT_TYPE_LCD, gdisp.screen[sel].iep_status & DRC_USED); Image_open(sel); DE_BE_EnableINT(sel, DE_IMG_REG_LOAD_FINISH); DE_BE_reg_auto_load_en(sel, 0); return DIS_SUCCESS; }
__s32 bsp_disp_capture_screen(__u32 screen_id, __disp_capture_screen_para_t * para) { __scal_buf_addr_t in_addr; __scal_buf_addr_t out_addr; __scal_src_size_t in_size; __scal_out_size_t out_size; __scal_src_type_t in_type; __scal_out_type_t out_type; __scal_scan_mod_t in_scan; __scal_scan_mod_t out_scan; __u32 size = 0; __s32 scaler_index = 0; __s32 ret = 0; if(para==NULL) { DE_WRN("input parameter can't be null!\n"); return DIS_FAIL; } scaler_index = Scaler_Request(0xff); if(scaler_index < 0) { DE_WRN("request scaler fail in bsp_disp_capture_screen\n"); return DIS_FAIL; } in_type.fmt= Scaler_sw_para_to_reg(0,DISP_MOD_INTERLEAVED, DISP_FORMAT_ARGB8888, DISP_SEQ_ARGB); in_type.mod= Scaler_sw_para_to_reg(1,DISP_MOD_INTERLEAVED, DISP_FORMAT_ARGB8888, DISP_SEQ_ARGB); in_type.ps= Scaler_sw_para_to_reg(2,DISP_MOD_INTERLEAVED, DISP_FORMAT_ARGB8888, (__u8)DISP_SEQ_ARGB); in_type.byte_seq = 0; in_type.sample_method = 0; if(get_fb_type(para->output_fb.format) == DISP_FB_TYPE_YUV) { if(para->output_fb.mode == DISP_MOD_NON_MB_PLANAR) { out_type.fmt = Scaler_sw_para_to_reg(3, para->output_fb.mode, para->output_fb.format, para->output_fb.seq); } else { DE_WRN("output mode:%d invalid in Display_Scaler_Start\n",para->output_fb.mode); return DIS_FAIL; } } else { if(para->output_fb.mode == DISP_MOD_NON_MB_PLANAR && (para->output_fb.format == DISP_FORMAT_RGB888 || para->output_fb.format == DISP_FORMAT_ARGB8888)) { out_type.fmt = DE_SCAL_OUTPRGB888; } else if(para->output_fb.mode == DISP_MOD_INTERLEAVED && para->output_fb.format == DISP_FORMAT_ARGB8888) { out_type.fmt = DE_SCAL_OUTI0RGB888; } else { DE_WRN("output para invalid in Display_Scaler_Start,mode:%d,format:%d\n",para->output_fb.mode, para->output_fb.format); return DIS_FAIL; } para->output_fb.br_swap= FALSE; } out_type.byte_seq = Scaler_sw_para_to_reg(2,para->output_fb.mode, para->output_fb.format, para->output_fb.seq); out_type.alpha_en = 1; out_type.alpha_coef_type = 0; out_size.width = para->output_fb.size.width; out_size.height = para->output_fb.size.height; if(bsp_disp_get_output_type(screen_id) != DISP_OUTPUT_TYPE_NONE) { in_size.src_width = bsp_disp_get_screen_width(screen_id); in_size.src_height = bsp_disp_get_screen_height(screen_id); in_size.x_off = 0; in_size.y_off = 0; in_size.scal_width= bsp_disp_get_screen_width(screen_id); in_size.scal_height= bsp_disp_get_screen_height(screen_id); } else { in_size.src_width = para->screen_size.width; in_size.src_height= para->screen_size.height; in_size.x_off = 0; in_size.y_off = 0; in_size.scal_width= para->screen_size.width; in_size.scal_height= para->screen_size.height; } in_scan.field = FALSE; in_scan.bottom = FALSE; out_scan.field = FALSE; //when use scaler as writeback, won't be outinterlaced for any display device out_scan.bottom = FALSE; in_addr.ch0_addr = 0; in_addr.ch1_addr = 0; in_addr.ch2_addr = 0; out_addr.ch0_addr = (__u32)OSAL_VAtoPA((void*)(para->output_fb.addr[0])); out_addr.ch1_addr = (__u32)OSAL_VAtoPA((void*)(para->output_fb.addr[1])); out_addr.ch2_addr = (__u32)OSAL_VAtoPA((void*)(para->output_fb.addr[2])); size = (para->output_fb.size.width * para->output_fb.size.height * de_format_to_bpp(para->output_fb.format) + 7)/8; OSAL_CacheRangeFlush((void *)para->output_fb.addr[0],size ,CACHE_FLUSH_D_CACHE_REGION); if(bsp_disp_get_output_type(screen_id) == DISP_OUTPUT_TYPE_NONE) { DE_SCAL_Input_Select(scaler_index, 6 + screen_id); DE_BE_set_display_size(screen_id, para->screen_size.width, para->screen_size.height); DE_BE_Output_Select(screen_id, 6 + scaler_index); image_clk_on(screen_id, 1); Image_open(screen_id); DE_BE_Cfg_Ready(screen_id); } else { DE_SCAL_Input_Select(scaler_index, 4 + screen_id); DE_BE_Output_Select(screen_id, 2 + (scaler_index * 2) + screen_id); } DE_SCAL_Config_Src(scaler_index,&in_addr,&in_size,&in_type,FALSE,FALSE); DE_SCAL_Set_Scaling_Factor(scaler_index, &in_scan, &in_size, &in_type, &out_scan, &out_size, &out_type); DE_SCAL_Set_Init_Phase(scaler_index, &in_scan, &in_size, &in_type, &out_scan, &out_size, &out_type, FALSE); DE_SCAL_Set_CSC_Coef(scaler_index, DISP_BT601, para->output_fb.cs_mode, DISP_FB_TYPE_RGB, get_fb_type(para->output_fb.format), 0, 0); DE_SCAL_Set_Scaling_Coef(scaler_index, &in_scan, &in_size, &in_type, &out_scan, &out_size, &out_type, DISP_VIDEO_NATUAL); DE_SCAL_Set_Out_Format(scaler_index, &out_type); DE_SCAL_Set_Out_Size(scaler_index, &out_scan,&out_type, &out_size); DE_SCAL_Set_Writeback_Addr(scaler_index,&out_addr); DE_SCAL_Output_Select(scaler_index, 3); DE_SCAL_ClearINT(scaler_index,DE_WB_END_IE); DE_SCAL_EnableINT(scaler_index,DE_WB_END_IE); DE_SCAL_Set_Reg_Rdy(scaler_index); DE_SCAL_Writeback_Enable(scaler_index); DE_SCAL_Start(scaler_index); DE_INF("capture begin\n"); #ifndef __LINUX_OSAL__ while(!(DE_SCAL_QueryINT(scaler_index) & DE_WB_END_IE)) { } #else { long timeout = (100 * HZ)/1000;//100ms init_waitqueue_head(&(gdisp.scaler[scaler_index].scaler_queue)); gdisp.scaler[scaler_index].b_scaler_finished = 1; DE_SCAL_Writeback_Enable(scaler_index); timeout = wait_event_interruptible_timeout(gdisp.scaler[scaler_index].scaler_queue, gdisp.scaler[scaler_index].b_scaler_finished == 2, timeout); gdisp.scaler[scaler_index].b_scaler_finished = 0; if(timeout == 0) { __wrn("wait scaler %d finished timeout\n", scaler_index); return -1; } } #endif DE_SCAL_Reset(scaler_index); Scaler_Release(scaler_index, FALSE); if(bsp_disp_get_output_type(screen_id) == DISP_OUTPUT_TYPE_NONE) { Image_close(screen_id); image_clk_off(screen_id, 1); } DE_BE_Output_Select(screen_id, screen_id); DE_SCAL_ClearINT(scaler_index,DE_WB_END_IE); DE_SCAL_DisableINT(scaler_index,DE_WB_END_IE); return ret; }
__s32 bsp_disp_tv_open(__u32 screen_id) { if(!(gdisp.screen[screen_id].status & TV_ON)) { __disp_tv_mode_t tv_mod; tv_mod = gdisp.screen[screen_id].tv_mode; image_clk_on(screen_id, 1); Image_open(screen_id);//set image normal channel start bit , because every de_clk_off( )will reset this bit disp_clk_cfg(screen_id,DISP_OUTPUT_TYPE_TV, tv_mod); tve_clk_on(screen_id); lcdc_clk_on(screen_id, 1, 0); lcdc_clk_on(screen_id, 1, 1); tcon_init(screen_id); gdisp.screen[screen_id].output_csc_type = DISP_OUT_CSC_TYPE_TV; bsp_disp_set_output_csc(screen_id, gdisp.screen[screen_id].output_csc_type, bsp_disp_drc_get_input_csc(screen_id)); DE_BE_set_display_size(screen_id, tv_mode_to_width(tv_mod), tv_mode_to_height(tv_mod)); DE_BE_Output_Select(screen_id, screen_id); #if (defined CONFIG_ARCH_SUN5I) __u32 scaler_index = 0; DE_BE_Set_Outitl_enable(screen_id , disp_get_screen_scan_mode(tv_mod)); for(scaler_index=0; scaler_index<2; scaler_index++) { if((gdisp.scaler[scaler_index].status & SCALER_USED) && (gdisp.scaler[scaler_index].screen_index == screen_id)) { if(disp_get_screen_scan_mode(tv_mod) == 1)//interlace output { Scaler_Set_Outitl(scaler_index, TRUE); } else { Scaler_Set_Outitl(scaler_index, FALSE); } } } #endif tcon1_set_tv_mode(screen_id,tv_mod); TVE_set_tv_mode(screen_id, tv_mod); Disp_TVEC_DacCfg(screen_id, tv_mod); tcon1_open(screen_id); Disp_TVEC_Open(screen_id); Disp_Switch_Dram_Mode(DISP_OUTPUT_TYPE_TV, tv_mod); #ifdef __LINUX_OSAL__ { disp_gpio_set_t gpio_info[1]; __hdle gpio_pa_shutdown; __s32 ret; memset(gpio_info, 0, sizeof(disp_gpio_set_t)); ret = OSAL_Script_FetchParser_Data("audio_para","audio_pa_ctrl", (int *)gpio_info, sizeof(disp_gpio_set_t)/sizeof(int)); if(ret == 0) { gpio_pa_shutdown = OSAL_GPIO_Request(gpio_info, 1); if(!gpio_pa_shutdown) { DE_WRN("audio codec_wakeup request gpio fail!\n"); } else { OSAL_GPIO_DevWRITE_ONEPIN_DATA(gpio_pa_shutdown, 0, "audio_pa_ctrl"); } } } #endif gdisp.screen[screen_id].b_out_interlace = disp_get_screen_scan_mode(tv_mod); gdisp.screen[screen_id].status |= TV_ON; gdisp.screen[screen_id].lcdc_status |= LCDC_TCON1_USED; gdisp.screen[screen_id].output_type = DISP_OUTPUT_TYPE_TV; #if (defined CONFIG_ARCH_SUN7I) Disp_set_out_interlace(screen_id); #endif #ifdef __LINUX_OSAL__ Display_set_fb_timming(screen_id); #endif } return DIS_SUCCESS; }
__s32 BSP_disp_tv_open(__u32 sel) { if (!(gdisp.screen[sel].status & TV_ON)) { __disp_tv_mode_t tv_mod; tv_mod = gdisp.screen[sel].tv_mode; image_clk_on(sel); /* * set image normal channel start bit , because every * de_clk_off( )will reset this bit */ Image_open(sel); disp_clk_cfg(sel, DISP_OUTPUT_TYPE_TV, tv_mod); tve_clk_on(sel); lcdc_clk_on(sel); BSP_disp_set_output_csc(sel, DISP_OUTPUT_TYPE_TV, gdisp.screen[sel]. iep_status & DRC_USED); DE_BE_set_display_size(sel, tv_mode_to_width(tv_mod), tv_mode_to_height(tv_mod)); DE_BE_Output_Select(sel, sel); if (sunxi_is_sun5i()) { int scaler_index; DE_BE_Set_Outitl_enable(sel, Disp_get_screen_scan_mode(tv_mod)); for (scaler_index = 0; scaler_index < 2; scaler_index++) if ((gdisp.scaler[scaler_index]. status & SCALER_USED) && (gdisp.scaler[scaler_index]. screen_index == sel)) { /* interlace output */ if (Disp_get_screen_scan_mode(tv_mod) == 1) Scaler_Set_Outitl(scaler_index, TRUE); else Scaler_Set_Outitl(scaler_index, FALSE); } } TCON1_set_tv_mode(sel, tv_mod); TVE_set_tv_mode(sel, tv_mod); Disp_TVEC_DacCfg(sel, tv_mod); TCON1_open(sel); Disp_TVEC_Open(sel); Disp_Switch_Dram_Mode(DISP_OUTPUT_TYPE_TV, tv_mod); Disp_de_flicker_enable(sel, TRUE); { user_gpio_set_t gpio_info[1]; __hdle gpio_pa_shutdown; __s32 ret; memset(gpio_info, 0, sizeof(user_gpio_set_t)); ret = script_parser_fetch("audio_para", "audio_pa_ctrl", (int *)gpio_info, sizeof(user_gpio_set_t) / sizeof(int)); if (ret < 0) { DE_WRN("fetch script data " "audio_para.audio_pa_ctrl fail\n"); } else { gpio_pa_shutdown = OSAL_GPIO_Request(gpio_info, 1); if (!gpio_pa_shutdown) { DE_WRN("audio codec_wakeup request " "gpio fail!\n"); } else { OSAL_GPIO_DevWRITE_ONEPIN_DATA (gpio_pa_shutdown, 0, "audio_pa_ctrl"); } } } gdisp.screen[sel].b_out_interlace = Disp_get_screen_scan_mode(tv_mod); gdisp.screen[sel].status |= TV_ON; gdisp.screen[sel].lcdc_status |= LCDC_TCON1_USED; gdisp.screen[sel].output_type = DISP_OUTPUT_TYPE_TV; Disp_set_out_interlace(sel); Display_set_fb_timing(sel); } return DIS_SUCCESS; }
__s32 bsp_disp_hdmi_open(__u32 screen_id) { if(disp_hdmi_get_support(screen_id) && (gdisp.screen[screen_id].hdmi_used) && (!(gdisp.screen[screen_id].status & HDMI_ON))) { __disp_tv_mode_t tv_mod; tv_mod = gdisp.screen[screen_id].hdmi_mode; hdmi_clk_on(); lcdc_clk_on(screen_id, 1, 0); lcdc_clk_on(screen_id, 1, 1); drc_clk_open(screen_id,0); drc_clk_open(screen_id,1); tcon_init(screen_id); image_clk_on(screen_id, 1); /* set image normal channel start bit , because every de_clk_off( )will reset this bit */ Image_open(screen_id); disp_clk_cfg(screen_id,DISP_OUTPUT_TYPE_HDMI, tv_mod); //bsp_disp_set_output_csc(screen_id, DISP_OUTPUT_TYPE_HDMI, gdisp.screen[screen_id].iep_status&DRC_USED); if(gdisp.init_para.hdmi_cts_compatibility == 0) { DE_INF("bsp_disp_hdmi_open: disable dvi mode\n"); bsp_disp_hdmi_dvi_enable(screen_id, 0); } else if(gdisp.init_para.hdmi_cts_compatibility == 1) { DE_INF("bsp_disp_hdmi_open: enable dvi mode\n"); bsp_disp_hdmi_dvi_enable(screen_id, 1); } else { bsp_disp_hdmi_dvi_enable(screen_id, bsp_disp_hdmi_dvi_support(screen_id)); } if(BSP_dsip_hdmi_get_input_csc(screen_id) == 0) { __inf("bsp_disp_hdmi_open: hdmi output rgb\n"); gdisp.screen[screen_id].output_csc_type = DISP_OUT_CSC_TYPE_HDMI_RGB; bsp_disp_set_output_csc(screen_id, gdisp.screen[screen_id].output_csc_type, bsp_disp_drc_get_input_csc(screen_id)); } else { __inf("bsp_disp_hdmi_open: hdmi output yuv\n"); gdisp.screen[screen_id].output_csc_type = DISP_OUT_CSC_TYPE_HDMI_YUV;//default yuv bsp_disp_set_output_csc(screen_id, gdisp.screen[screen_id].output_csc_type, bsp_disp_drc_get_input_csc(screen_id)); } DE_BE_set_display_size(screen_id, tv_mode_to_width(tv_mod), tv_mode_to_height(tv_mod)); DE_BE_Output_Select(screen_id, screen_id); bsp_disp_hdmi_set_src(screen_id, DISP_LCDC_SRC_DE_CH1); tcon1_set_hdmi_mode(screen_id,tv_mod); tcon1_open(screen_id); if(gdisp.init_para.hdmi_open) { gdisp.init_para.hdmi_open(); } else { DE_WRN("Hdmi_open is NULL\n"); return -1; } Disp_Switch_Dram_Mode(DISP_OUTPUT_TYPE_HDMI, tv_mod); gdisp.screen[screen_id].b_out_interlace = disp_get_screen_scan_mode(tv_mod); gdisp.screen[screen_id].status |= HDMI_ON; gdisp.screen[screen_id].lcdc_status |= LCDC_TCON1_USED; gdisp.screen[screen_id].output_type = DISP_OUTPUT_TYPE_HDMI; if(bsp_disp_cmu_get_enable(screen_id) ==1) { IEP_CMU_Set_Imgsize(screen_id, bsp_disp_get_screen_width(screen_id), bsp_disp_get_screen_height(screen_id)); } Disp_set_out_interlace(screen_id); #ifdef __LINUX_OSAL__ Display_set_fb_timming(screen_id); #endif return DIS_SUCCESS; } return DIS_NOT_SUPPORT; }
__s32 BSP_disp_tv_open(__u32 sel) { if(!(gdisp.screen[sel].status & TV_ON)) { __disp_tv_mode_t tv_mod; tv_mod = gdisp.screen[sel].tv_mode; image_clk_on(sel); Image_open(sel);//set image normal channel start bit , because every de_clk_off( )will reset this bit disp_clk_cfg(sel,DISP_OUTPUT_TYPE_TV, tv_mod); tve_clk_on(sel); lcdc_clk_on(sel); BSP_disp_set_output_csc(sel, DISP_OUTPUT_TYPE_TV); DE_BE_set_display_size(sel, tv_mode_to_width(tv_mod), tv_mode_to_height(tv_mod)); DE_BE_Output_Select(sel, sel); TCON1_set_tv_mode(sel,tv_mod); TVE_set_tv_mode(sel, tv_mod); Disp_TVEC_DacCfg(sel, tv_mod); TCON1_open(sel); Disp_TVEC_Open(sel); Disp_Switch_Dram_Mode(DISP_OUTPUT_TYPE_TV, tv_mod); #ifdef __LINUX_OSAL__ { user_gpio_set_t gpio_info[1]; __hdle gpio_pa_shutdown; __s32 ret; memset(gpio_info, 0, sizeof(user_gpio_set_t)); ret = OSAL_Script_FetchParser_Data("audio_para","audio_pa_ctrl", (int *)gpio_info, sizeof(user_gpio_set_t)/sizeof(int)); if(ret < 0) { DE_WRN("fetch script data audio_para.audio_pa_ctrl fail\n"); } else { gpio_pa_shutdown = OSAL_GPIO_Request(gpio_info, 1); if(!gpio_pa_shutdown) { DE_WRN("audio codec_wakeup request gpio fail!\n"); } else { OSAL_GPIO_DevWRITE_ONEPIN_DATA(gpio_pa_shutdown, 0, "audio_pa_ctrl"); } } } #endif gdisp.screen[sel].b_out_interlace = Disp_get_screen_scan_mode(tv_mod); gdisp.screen[sel].status |= TV_ON; gdisp.screen[sel].lcdc_status |= LCDC_TCON1_USED; gdisp.screen[sel].output_type = DISP_OUTPUT_TYPE_TV; Disp_set_out_interlace(sel); #ifdef __LINUX_OSAL__ Display_set_fb_timming(sel); #endif } return DIS_SUCCESS; }
__s32 BSP_disp_hdmi_open(__u32 sel) { if(!(gdisp.screen[sel].status & HDMI_ON)) { __disp_tv_mode_t tv_mod; tv_mod = gdisp.screen[sel].hdmi_mode; BSP_disp_hdmi_get_hdcp_enable(); hdmi_clk_on(); if(gdisp.screen[sel].hdmi_hdcp_en) hdcp_clk_init(tv_mod); lcdc_clk_on(sel, 1, 0); lcdc_clk_on(sel, 1, 1); Disp_lcdc_reg_isr(sel); LCDC_init(sel); image_clk_on(sel, 0); image_clk_on(sel, 1); Image_open(sel);//set image normal channel start bit , because every de_clk_off( )will reset this bit DE_BE_EnableINT(sel, DE_IMG_REG_LOAD_FINISH); disp_clk_cfg(sel,DISP_OUTPUT_TYPE_HDMI, tv_mod); if(gdisp.init_para.hdmi_cts_compatibility == 0) { DE_INF("BSP_disp_hdmi_open: disable dvi mode\n"); BSP_disp_hdmi_dvi_enable(sel, 0); } else if(gdisp.init_para.hdmi_cts_compatibility == 1) { DE_INF("BSP_disp_hdmi_open: enable dvi mode\n"); BSP_disp_hdmi_dvi_enable(sel, 1); } else { BSP_disp_hdmi_dvi_enable(sel, BSP_disp_hdmi_dvi_support(sel)); } if(BSP_dsip_hdmi_get_input_csc(sel) == 0) { __inf("BSP_disp_hdmi_open: hdmi output rgb\n"); gdisp.screen[sel].output_csc_type = DISP_OUT_CSC_TYPE_HDMI_RGB; BSP_disp_set_output_csc(sel, gdisp.screen[sel].output_csc_type); }else { __inf("BSP_disp_hdmi_open: hdmi output yuv\n"); gdisp.screen[sel].output_csc_type = DISP_OUT_CSC_TYPE_HDMI_YUV;//default yuv BSP_disp_set_output_csc(sel, gdisp.screen[sel].output_csc_type); } DE_BE_set_display_size(sel, tv_mode_to_width(tv_mod), tv_mode_to_height(tv_mod)); DE_BE_Output_Select(sel, sel); tcon1_set_hdmi_mode(sel,tv_mod); tcon1_open(sel); if(gdisp.init_para.hdmi_open) { gdisp.init_para.hdmi_open(); } else { DE_WRN("hdmi_open is NULL\n"); return -1; } Disp_Switch_Dram_Mode(DISP_OUTPUT_TYPE_HDMI, tv_mod); gdisp.screen[sel].b_out_interlace = Disp_get_screen_scan_mode(tv_mod); gdisp.screen[sel].status |= HDMI_ON; gdisp.screen[sel].lcdc_status |= LCDC_TCON1_USED; gdisp.screen[sel].output_type = DISP_OUTPUT_TYPE_HDMI; Disp_set_out_interlace(sel); #ifdef __LINUX_OSAL__ Display_set_fb_timming(sel); #endif } return DIS_SUCCESS; }