void sm511_device::get_opcode_param()
{
// XXX?, LBL, PRE, TL, TML and prefix opcodes are 2 bytes
if (m_op == 0x01 || (m_op >= 0x5f && m_op <= 0x61) || (m_op & 0xf0) == 0x70 || (m_op & 0xfc) == 0x68)
{
m_icount--;
m_param = m_program->read_byte(m_pc);
increment_pc();
}
}
inline void ucom4_cpu_device::fetch_arg()
{
// 2-byte opcodes: STM/LDI/CLI/CI, JMP/CAL, OCD
if ((m_op & 0xfc) == 0x14 || (m_op & 0xf0) == 0xa0 || m_op == 0x1e)
{
m_icount--;
m_arg = m_program->read_byte(m_pc);
increment_pc();
}
}
void sm510_device::get_opcode_param()
{
// LBL, TL, TML opcodes are 2 bytes
if (m_op == 0x5f || (m_op & 0xf0) == 0x70)
{
m_icount--;
m_param = m_program->read_byte(m_pc);
increment_pc();
}
}
void sm510_base_device::get_opcode_param()
{
// LBL, TL, TML, TM opcodes are 2 bytes
if (m_op == 0x5f || (m_op & 0xf0) == 0x70 || m_op >= 0xc0)
{
m_icount -= 2; // guessed
m_param = m_program->read_byte(m_pc);
increment_pc();
}
}
sm510_common_disassembler::sm510_common_disassembler()
{
// init 6-bit lfsr pc lut
for (u32 i = 0, pc = 0; i < 0x3f; i++)
{
m_l2r6[i] = pc;
m_r2l6[pc] = i;
pc = increment_pc(pc, 6);
}
m_l2r6[0x3f] = 0x3f;
m_r2l6[0x3f] = 0x3f;
// init 7-bit lfsr pc lut
for (u32 i = 0, pc = 0; i < 0x7f; i++)
{
m_l2r7[i] = pc;
m_r2l7[pc] = i;
pc = increment_pc(pc, 7);
}
m_l2r7[0x7f] = 0x7f;
m_r2l7[0x7f] = 0x7f;
}
void sm510_base_device::execute_run()
{
while (m_icount > 0)
{
// remember previous state
m_prev_op = m_op;
m_prev_pc = m_pc;
// fetch next opcode
debugger_instruction_hook(this, m_pc);
m_icount -= 2; // 61us typical
m_op = m_program->read_byte(m_pc);
increment_pc();
get_opcode_param();
// handle opcode
}
}
void powerpc_cpu::execute_illegal(uint32 opcode)
{
fprintf(stderr, "Illegal instruction at %08x, opcode = %08x\n", pc(), opcode);
#ifdef SHEEPSHAVER
if (PrefsFindBool("ignoreillegal")) {
increment_pc(4);
return;
}
#endif
#if ENABLE_MON
disass_ppc(stdout, pc(), opcode);
// Start up mon in real-mode
char *arg[4] = {"mon", "-m", "-r", NULL};
mon(3, arg);
#endif
abort();
}
void Debugger::RunDebuggerShell() {
if (IsDebuggerRunning()) {
if (steps_ > 0) {
// Finish stepping first.
--steps_;
return;
}
printf("Next: ");
PrintInstructions(pc());
bool done = false;
while (!done) {
char buffer[kMaxDebugShellLine];
char* line = ReadCommandLine("vixl> ", buffer, kMaxDebugShellLine);
if (line == NULL) continue; // An error occurred.
DebugCommand* command = DebugCommand::Parse(line);
if (command != NULL) {
last_command_ = command;
}
if (last_command_ != NULL) {
done = last_command_->Run(this);
} else {
printf("No previous command to run!\n");
}
}
if ((debug_parameters_ & DBG_BREAK) != 0) {
// The break request has now been handled, move to next instruction.
debug_parameters_ &= ~DBG_BREAK;
increment_pc();
}
}
}
void powerpc_cpu::execute_nop(uint32 opcode)
{
increment_pc(4);
}
void ucom4_cpu_device::execute_run()
{
while (m_icount > 0)
{
m_icount--;
// remember previous opcode
m_prev_op = m_op;
// handle interrupt - it not accepted during LI($9x) or EI($31), or while skipping
if (m_int_f && m_inte_f && (m_prev_op & 0xf0) != 0x90 && m_prev_op != 0x31 && !m_skip)
{
m_icount--;
push_stack();
m_pc = 0xf << 2;
m_int_f = 0;
m_inte_f = (m_family == NEC_UCOM43) ? 0 : 1;
standard_irq_callback(0);
}
// fetch next opcode
debugger_instruction_hook(this, m_pc);
m_op = m_program->read_byte(m_pc);
m_bitmask = 1 << (m_op & 0x03);
increment_pc();
fetch_arg();
if (m_skip)
{
m_skip = false;
m_op = 0; // nop
}
// handle opcode
switch (m_op & 0xf0)
{
case 0x80: op_ldz(); break;
case 0x90: op_li(); break;
case 0xa0: op_jmpcal(); break;
case 0xb0: op_czp(); break;
case 0xc0: case 0xd0: case 0xe0: case 0xf0: op_jcp(); break;
default:
switch (m_op)
{
case 0x00: op_nop(); break;
case 0x01: op_di(); break;
case 0x02: op_s(); break;
case 0x03: op_tit(); break;
case 0x04: op_tc(); break;
case 0x05: op_ttm(); break;
case 0x06: op_daa(); break;
case 0x07: op_tal(); break;
case 0x08: op_ad(); break;
case 0x09: op_ads(); break;
case 0x0a: op_das(); break;
case 0x0b: op_clc(); break;
case 0x0c: op_cm(); break;
case 0x0d: op_inc(); break;
case 0x0e: op_op(); break;
case 0x0f: op_dec(); break;
case 0x10: op_cma(); break;
case 0x11: op_cia(); break;
case 0x12: op_tla(); break;
case 0x13: op_ded(); break;
case 0x14: op_stm(); break;
case 0x15: op_ldi(); break;
case 0x16: op_cli(); break;
case 0x17: op_ci(); break;
case 0x18: op_exl(); break;
case 0x19: op_adc(); break;
case 0x1a: op_xc(); break;
case 0x1b: op_stc(); break;
case 0x1c: op_illegal(); break;
case 0x1d: op_inm(); break;
case 0x1e: op_ocd(); break;
case 0x1f: op_dem(); break;
case 0x30: op_rar(); break;
case 0x31: op_ei(); break;
case 0x32: op_ip(); break;
case 0x33: op_ind(); break;
case 0x40: op_ia(); break;
case 0x41: op_jpa(); break;
case 0x42: op_taz(); break;
case 0x43: op_taw(); break;
case 0x44: op_oe(); break;
case 0x45: op_illegal(); break;
case 0x46: op_tly(); break;
case 0x47: op_thx(); break;
case 0x48: op_rt(); break;
case 0x49: op_rts(); break;
case 0x4a: op_xaz(); break;
case 0x4b: op_xaw(); break;
case 0x4c: op_xls(); break;
case 0x4d: op_xhr(); break;
case 0x4e: op_xly(); break;
case 0x4f: op_xhx(); break;
default:
switch (m_op & 0xfc)
{
case 0x20: op_fbf(); break;
case 0x24: op_tab(); break;
case 0x28: op_xm(); break;
case 0x2c: op_xmd(); break;
case 0x34: op_cmb(); break;
case 0x38: op_lm(); break;
case 0x3c: op_xmi(); break;
case 0x50: op_tpb(); break;
case 0x54: op_tpa(); break;
case 0x58: op_tmb(); break;
case 0x5c: op_fbt(); break;
case 0x60: op_rpb(); break;
case 0x64: op_reb(); break;
case 0x68: op_rmb(); break;
case 0x6c: op_rfb(); break;
case 0x70: op_spb(); break;
case 0x74: op_seb(); break;
case 0x78: op_smb(); break;
case 0x7c: op_sfb(); break;
}
break; // 0xfc
}
break; // 0xff
} // big switch
}
}
