void ompl::control::Syclop::buildGraph(void)
{
VertexIndexMap index = get(boost::vertex_index, graph_);
std::vector<int> neighbors;
for (int i = 0; i < decomp_->getNumRegions(); ++i)
{
const RegionGraph::vertex_descriptor v = boost::add_vertex(graph_);
Region& r = graph_[boost::vertex(v,graph_)];
initRegion(r);
r.index = index[v];
}
VertexIter vi, vend;
for (boost::tie(vi,vend) = boost::vertices(graph_); vi != vend; ++vi)
{
/* Create an edge between this vertex and each of its neighboring regions in the decomposition,
and initialize the edge's Adjacency object. */
decomp_->getNeighbors(index[*vi], neighbors);
for (std::vector<int>::const_iterator j = neighbors.begin(); j != neighbors.end(); ++j)
{
RegionGraph::edge_descriptor edge;
bool ignore;
boost::tie(edge, ignore) = boost::add_edge(*vi, boost::vertex(*j,graph_), graph_);
initEdge(graph_[edge], &graph_[*vi], &graph_[boost::vertex(*j,graph_)]);
}
neighbors.clear();
}
}
int main()
{
int t;
char s[MAXN];
scanf("%d", &t);
for(int k=1; k<=t; ++k)
{
scanf("%d", &n);
initEdge();
for(int i=0; i<n; ++i)
{
scanf("%s", s);
for(int j=0; j<n; ++j)
{
if(s[j] == '1')
{
addEdge(i, j);
}
}
}
bool flag = false;
memset(visit, false, sizeof(visit));
memset(record, false, sizeof(record));
for(int i=0; i<n && !flag; ++i)
{
if(!visit[i])
{
if(dfs(i, 0))
{
flag = true;
break;
}
}
}
printf("Case #%d: ", k);
if(flag)
{
printf("Yes\n");
}
else
{
printf("No\n");
}
}
return 0;
}
void addEdge (int src, int dst, int wt) {
if (wt == 0) return;
edge_p_t edge = initEdge(src, dst, wt);
G->edges[ec++] = edge;
}
void Trace::processEther(bool doBasicBlocks)
{
FILE *fin = NULL;
char in[LINELEN] = {0};
char lastline[LINELEN] = {0};
char addr[ADDRLEN] = {0};
char inst[INSTLEN] = {0};
uint32_t daddr = 0;
unsigned long lines = 0;
uint32_t inum = 0;
uint32_t bblnum = 0;
uint32_t lastbbl = 0;
uint32_t edgenum = 0;
memset(in, 0, sizeof(in));
memset(lastline, 0, sizeof(lastline));
memset(addr, 0, sizeof(addr));
memset(inst, 0, sizeof(inst));
bool inInstructions = false;
bool isFirstAddr = true;
bool inBranch = false;
fin = fopen(this->tracefile, "r");
if(fin == NULL)
{
//wxLogDebug(wxT("Error opening file %s\n"), this->tracefile);
return;
}
//wxLogDebug(wxT("%s opened successfully\n"), this->tracefile);
// Add the start basic block and edge
initAddress(&bblMap[START_ADDR], START_ADDR, (char *) "START", 1, bblnum++);
lastbbl = START_ADDR;
while(fgets(in, sizeof(in)-1, fin) != NULL)
{
// if the lines are the same, skip it. Ether is weird like that
if(strcmp(in, lastline) == 0)
continue;
else
strncpy(lastline, in, sizeof(lastline));
// This marks the beginning of the instructions
if(!inInstructions && (strstr(in, "Entry Point:") ))
{
inInstructions = true;
#ifdef _WIN32
sscanf_s(in, "%*s%*s%s", addr, sizeof(addr));
#else
sscanf(in, "%*s%*s%31s", addr);
#endif
//wxLogDebug(wxT("Entry point: %s\n"), addr);
continue;
}
else if (!inInstructions && isAddressLine(in))
{
inInstructions = true;
sscanf(in, "%s:", addr);
continue;
}
else if (!inInstructions)
{
continue;
}
// Check for an end condition
if(strstr(in, "Handling sigint"))
break;
// If we are over the limit on instruction size then cap it at INSTLEN
size_t inlen = strlen(in) > INSTLEN ? INSTLEN : strlen(in);
size_t j = 0;
size_t i;
// read in the address
for(i = 0 ; i < inlen ; i++)
{
if (in[i] == ':' || in[i] == ' ' || in[i] == '\t' || in[i] == '\0')
break;
if (in[i] != ':' && j < inlen)
addr[j++] = in[i];
}
addr[j] = '\0';
// skip the ": "
i += 2;
j = 0;
// read in the instruction
while(i < inlen)
{
// Fix the tab to be a space
if( in[i] == '\t' )
in[i] = ' ';
inst[j++] = in[i++];
}
inst[j] = '\0';
xtoi(addr, &daddr);
if(doBasicBlocks)
{
if (isFirstAddr)
{
// The first address is always the beginning of a basic block.
// It stays that way until a branch is seen
// What about if the first instruction is a branch instruction?
initAddress(&bblMap[daddr], daddr, inst, 0, bblnum++);
initEdge(&edgeMap[MAKE_EDGE_KEY(START_ADDR, daddr)], START_ADDR, daddr, 1, edgenum++);
isFirstAddr = false;
lastbbl = daddr;
orderVector.push_back(daddr);
}
else if (!inBranch && branchMatch(inst))
{
// If we're not presently in a branch and come to a branch instruction
// setup for a new basic block
inBranch = true;
}
else if (inBranch)
{
// In a branch and we come to another branch instruction.
// allocate the memory and end it off
// Example:
// jmp ADDR1
// ADDR1:
// jmp ADDR2 <-- this is where we'd be at
if(bblMap.find(daddr) != bblMap.end())
{
bblMap[daddr].count++;
}
else
{
initAddress(&bblMap[daddr], daddr, inst, 0, bblnum++);
}
orderVector.push_back(daddr);
// Add an edge to the edge list
// current = daddr
// last = lastbbl
unsigned long long edgekey = 0;
edgekey = MAKE_EDGE_KEY(lastbbl, daddr);
// Add the edge to the list
if(edgeMap.find(edgekey) != edgeMap.end())
edgeMap[edgekey].count++;
else
initEdge(&edgeMap[edgekey], GET_SRC_FROM_EDGE_KEY(edgekey),
GET_DST_FROM_EDGE_KEY(edgekey),
1,
edgenum++);
lastbbl = daddr;
// Setup the instruction states
if (branchMatch(inst))
inBranch = true;
else
inBranch = false;
}
}
else // Process all addresses
{
if (isFirstAddr)
{
initAddress(&bblMap[daddr], daddr, inst, 0, bblnum++);
initEdge(&edgeMap[MAKE_EDGE_KEY(START_ADDR, daddr)], START_ADDR, daddr, 1, edgenum++);
isFirstAddr = false;
lastbbl = daddr;
orderVector.push_back(daddr);
}
else
{
if(bblMap.find(daddr) != bblMap.end())
{
bblMap[daddr].count++;
}
else
{
initAddress(&bblMap[daddr], daddr, inst, 0, bblnum++);
}
orderVector.push_back(daddr);
unsigned long long edgekey = 0;
edgekey = MAKE_EDGE_KEY(lastbbl, daddr);
// Add the edge to the list
if(edgeMap.find(edgekey) != edgeMap.end())
edgeMap[edgekey].count++;
else
initEdge(&edgeMap[edgekey],
GET_SRC_FROM_EDGE_KEY(edgekey),
GET_DST_FROM_EDGE_KEY(edgekey),
1,
edgenum++);
lastbbl = daddr;
}
}
inum++;
lines++;
memset(in, 0, sizeof(in));
}
fclose(fin);
//wxLogDebug(wxT("Analyzed %u instructions with %u basic blocks.\n"), inum, bblnum);
}
void Trace::processVeraPin(bool doBasicBlocks)
{
//wxLogDebug(wxT("Trace::processVeraPin stub handler\n"));
//if (doBasicBlocks)
// return;
wchar_t widein[LINELEN] = {0};
char in[LINELEN] = {0};
char addr[ADDRLEN] = {0};
char api[APILEN] = {0};
char inst[APILEN] = {0};
FILE *fin = NULL;
size_t charconverted = 0;
uint32_t daddr = 0;
uint32_t lastbbl = 0;
unsigned long lines = 0;
uint32_t inum = 0;
uint32_t bblnum = 0;
uint32_t edgenum = 0;
char *pos = NULL;
bool isFirstAddr = true;
bool isImport = false;
fin = fopen(this->tracefile, "r");
if (fin == 0)
return;
initAddress(&bblMap[START_ADDR], START_ADDR, (char *) "START", 1, bblnum++);
while (fgetws(widein, sizeof(widein)-1, fin) != NULL)
{
wcstombs(in, widein, sizeof(in));
switch (in[0])
{
case 'm':
case 'n':
// Just get the normal instructions
parseTraceLine(&in[1], addr, sizeof(addr), inst, sizeof(inst));
isImport = false;
break;
case 'i':
// Handle a detected import string
parseTraceLine(&in[1], addr, sizeof(addr), api, sizeof(api));
isImport = true;
break;
default:
// normal
break;
}
// Skip the version string.
if (wcsstr(widein, L"vera_trace_version=") == widein)
continue;
xtoi(addr, &daddr);
orderVector.push_back(daddr);
if (isFirstAddr)
{
initAddress(&bblMap[daddr], daddr, (isImport == true ? api : inst), 0, bblnum++);
initEdge(&edgeMap[MAKE_EDGE_KEY(START_ADDR, daddr)], START_ADDR, daddr, 1, edgenum++);
isFirstAddr = false;
lastbbl = daddr;
}
else
{
if(bblMap.find(daddr) != bblMap.end())
{
bblMap[daddr].count++;
}
else
{
initAddress(&bblMap[daddr], daddr, (char *) (isImport == true ? api : inst), 0, bblnum++);
bblMap[daddr].isApi = isImport;
}
uint64_t edgekey = 0;
edgekey = MAKE_EDGE_KEY(lastbbl, daddr);
// Add the edge to the list
if(edgeMap.find(edgekey) != edgeMap.end())
edgeMap[edgekey].count++;
else
initEdge(&edgeMap[edgekey],
(uint32_t) GET_SRC_FROM_EDGE_KEY(edgekey),
(uint32_t) GET_DST_FROM_EDGE_KEY(edgekey),
(uint32_t) 1,
edgenum++);
lastbbl = daddr;
}
inum++;
lines++;
}
fclose(fin);
}
