composite_t *new_or_composite(uint32_t n, occ_t *a) {
composite_t *tmp;
tmp = alloc_composite(n);
init_or(tmp, n, a);
return tmp;
}
composite_t *arena_or_composite(arena_t *m, uint32_t n, occ_t *a) {
composite_t *tmp;
tmp = arena_alloc_composite(m, n);
init_or(tmp, n, a);
return tmp;
}
static inline u32
init_nvreg(struct nvbios_init *init, u32 reg)
{
/* C51 (at least) sometimes has the lower bits set which the VBIOS
* interprets to mean that access needs to go through certain IO
* ports instead. The NVIDIA binary driver has been seen to access
* these through the NV register address, so lets assume we can
* do the same
*/
reg &= ~0x00000003;
/* GF8+ display scripts need register addresses mangled a bit to
* select a specific CRTC/OR
*/
if (nv_device(init->bios)->card_type >= NV_50) {
if (reg & 0x80000000) {
reg += init_crtc(init) * 0x800;
reg &= ~0x80000000;
}
if (reg & 0x40000000) {
reg += init_or(init) * 0x800;
reg &= ~0x40000000;
if (reg & 0x20000000) {
reg += init_link(init) * 0x80;
reg &= ~0x20000000;
}
}
}
if (reg & ~0x00fffffc)
warn("unknown bits in register 0x%08x\n", reg);
return reg;
}
