void
db_restart_at_pc(db_regs_t *regs, bool watchpt)
{
db_addr_t pc = PC_REGS(regs);
#ifdef SOFTWARE_SSTEP
db_addr_t brpc;
#endif
if ((db_run_mode == STEP_COUNT) ||
(db_run_mode == STEP_RETURN) ||
(db_run_mode == STEP_CALLT)) {
db_expr_t ins __unused;
/*
* We are about to execute this instruction,
* so count it now.
*/
ins = db_get_value(pc, sizeof(int), false);
db_inst_count++;
db_load_count += inst_load(ins);
db_store_count += inst_store(ins);
#ifdef SOFTWARE_SSTEP
/*
* Account for instructions in delay slots.
*/
brpc = next_instr_address(pc, true);
if ((brpc != pc) &&
(inst_branch(ins) || inst_call(ins) || inst_return(ins))) {
ins = db_get_value(brpc, sizeof(int), false);
db_inst_count++;
db_load_count += inst_load(ins);
db_store_count += inst_store(ins);
}
#endif
}
if (db_run_mode == STEP_CONTINUE) {
if (watchpt || db_find_breakpoint_here(pc)) {
/*
* Step over breakpoint/watchpoint.
*/
db_run_mode = STEP_INVISIBLE;
db_set_single_step(regs);
} else {
db_set_breakpoints();
db_set_watchpoints();
}
} else {
db_set_single_step(regs);
}
}
static int
inst_BIT(struct OPCodeDesc *op, struct machine *m)
{
inst_load(m);
byte amp = m->cpu.dbb & m->cpu.reg.ac;
if (m->cpu.dbb & BYTE_SIGN_MASK)
SR_N_SET(m->cpu.reg.sr);
else
SR_N_CLR(m->cpu.reg.sr);
if (m->cpu.dbb & (BYTE_SIGN_MASK-1))
SR_V_SET(m->cpu.reg.sr);
else
SR_V_CLR(m->cpu.reg.sr);
if (amp == 0x00)
SR_Z_SET(m->cpu.reg.sr);
else
SR_Z_CLR(m->cpu.reg.sr);
return 1;
}
void
db_restart_at_pc(boolean_t watchpt)
{
db_addr_t pc = PC_REGS(DDB_REGS);
if ((db_run_mode == STEP_COUNT) ||
(db_run_mode == STEP_RETURN) ||
(db_run_mode == STEP_CALLT)) {
db_expr_t ins __unused; /* seems used but gcc thinks not */
/*
* We are about to execute this instruction,
* so count it now.
*/
ins = db_get_value(pc, sizeof(int), FALSE);
db_inst_count++;
db_load_count += inst_load(ins);
db_store_count += inst_store(ins);
#ifdef SOFTWARE_SSTEP
/* XXX works on mips, but... */
if (inst_branch(ins) || inst_call(ins)) {
ins = db_get_value(next_instr_address(pc,1),
sizeof(int), FALSE);
db_inst_count++;
db_load_count += inst_load(ins);
db_store_count += inst_store(ins);
}
#endif /* SOFTWARE_SSTEP */
}
if (db_run_mode == STEP_CONTINUE) {
if (watchpt || db_find_breakpoint_here(pc)) {
/*
* Step over breakpoint/watchpoint.
*/
db_run_mode = STEP_INVISIBLE;
db_set_single_step(DDB_REGS);
} else {
db_set_breakpoints();
db_set_watchpoints();
}
} else {
db_set_single_step(DDB_REGS);
}
}
static int
inst_BPL(struct OPCodeDesc *op, struct machine *m)
{
if(!SR_N(m->cpu.reg.sr)){
inst_load(m);
m->cpu.reg.pc += (signed char) m->cpu.dbb;
}
return 1;
}
static int
inst_LDX(struct OPCodeDesc *op, struct machine *m)
{
inst_load(m);
m->cpu.reg.x = m->cpu.dbb;
if (m->cpu.reg.x == 0)
SR_Z_SET(m->cpu.reg.sr);
else
SR_Z_CLR(m->cpu.reg.sr);
if (m->cpu.reg.x & BYTE_SIGN_MASK)
SR_N_SET(m->cpu.reg.sr);
else
SR_N_CLR(m->cpu.reg.sr);
return 1;
}
static int
inst_ADC(struct OPCodeDesc *op, struct machine *m)
{
inst_load(m);
byte val = m->cpu.dbb;
byte temp = m->cpu.reg.ac + (val + SR_C(m->cpu.reg.sr));
if (SR_D(m->cpu.reg.sr)) {
NYI;
}
SR_Z_CLR(m->cpu.reg.sr);
SR_V_CLR(m->cpu.reg.sr);
SR_C_CLR(m->cpu.reg.sr);
SR_N_CLR(m->cpu.reg.sr);
if( temp > 0xFF )
SR_C_SET(m->cpu.reg.sr);
if (!((m->cpu.reg.ac ^ val) & BYTE_SIGN_MASK) && ((m->cpu.reg.ac ^ temp) & BYTE_SIGN_MASK))
SR_V_SET(m->cpu.reg.sr);
m->cpu.reg.ac = temp & 0xFF;
if( m->cpu.reg.ac & BYTE_SIGN_MASK )
SR_N_SET(m->cpu.reg.sr);
if(m->cpu.reg.ac == 0)
SR_Z_SET(m->cpu.reg.sr);
return 1;
}
static int
inst_INC(struct OPCodeDesc *op, struct machine *m)
{
inst_load(m);
m->cpu.dbb++;
if (m->cpu.dbb == 0)
SR_Z_SET(m->cpu.reg.sr);
else
SR_Z_CLR(m->cpu.reg.sr);
if (m->cpu.dbb & BYTE_SIGN_MASK)
SR_N_SET(m->cpu.reg.sr);
else
SR_N_CLR(m->cpu.reg.sr);
inst_store(m);
return 1;
// NYI; dump_op(op); dump_reg(m); assert(0); return 0;
}
static int
inst_CPY(struct OPCodeDesc *op, struct machine *m)
{
inst_load(m);
if (m->cpu.dbb <= m->cpu.reg.y)
SR_C_SET(m->cpu.reg.sr);
else
SR_C_CLR(m->cpu.reg.sr);
if ((m->cpu.reg.y - m->cpu.dbb) & BYTE_SIGN_MASK)
SR_N_SET(m->cpu.reg.sr);
else
SR_N_CLR(m->cpu.reg.sr);
if (m->cpu.dbb == m->cpu.reg.y)
SR_Z_SET(m->cpu.reg.sr);
else
SR_Z_CLR(m->cpu.reg.sr);
return 1;
}
static int
inst_ASL(struct OPCodeDesc *op, struct machine *m)
{
if (op->am->mode == ACC) {
if(m->cpu.reg.ac & BYTE_SIGN_MASK)
SR_C_SET(m->cpu.reg.sr);
else
SR_C_CLR(m->cpu.reg.sr);
m->cpu.reg.ac <<= 1;
m->cpu.reg.ac &= 0xFF;
if(m->cpu.reg.ac & BYTE_SIGN_MASK) {
SR_N_SET(m->cpu.reg.sr);
} else
SR_N_CLR(m->cpu.reg.sr);
if (m->cpu.reg.ac == 0)
SR_Z_SET(m->cpu.reg.sr);
else
SR_Z_CLR(m->cpu.reg.sr);
return 1;
}
else {
inst_load(m);
if(m->cpu.dbb & BYTE_SIGN_MASK)
SR_C_SET(m->cpu.reg.sr);
else
SR_C_CLR(m->cpu.reg.sr);
m->cpu.dbb <<= 1;
m->cpu.dbb &= 0xFF;
if(m->cpu.dbb & BYTE_SIGN_MASK) {
SR_N_SET(m->cpu.reg.sr); }
else
SR_N_CLR(m->cpu.reg.sr);
if (m->cpu.dbb == 0)
SR_Z_SET(m->cpu.reg.sr);
else
SR_Z_CLR(m->cpu.reg.sr);
inst_store(m);
return 1;
}
}