/**************************************************************************//**
* @brief This function initializes key GPIO as input pullup and disables
* interrupts. If \e ui8Mode is \b BSP_KEY_MODE_POLL, key presses are
* handled using polling and active state debounce. Functions starting
* with \b bspKeyInt then do nothing.
*
* If \e ui8Mode is \b BSP_KEY_MODE_ISR, key presses are handled by
* interrupts, and debounce is implemented using the watchdog timer.
*
* @note If \b BSP_KEY_NO_ISR is defined, parameter \e ui8Mode
* is ignored and key presses are handled using polling and active
* state debounce. In this case the watchdog timer interrupt vector
* is not assigned to an interrupt handler.
*
* @param ui8Mode is the operating; it must be one of the following:
* \li \b BSP_KEY_MODE_POLL for polling-based handling
* \li \b BSP_KEY_MODE_ISR for interrupt-based handling
******************************************************************************/
void
bspKeyInit(uint8_t ui8Mode)
{
//
// Store mode
//
#ifndef BSP_KEY_NO_ISR
ui8BspKeyMode = ui8Mode;
#else
ui8BspKeyMode = BSP_KEY_MODE_POLL;
#endif
#if defined(__MSP430F5428A__)
//
// Initialize keys as GPIO input pullup:
//
BSP_KEY_SEL &= ~(BSP_KEY_ALL);
BSP_KEY_DIR &= ~(BSP_KEY_ALL);
BSP_KEY_OUT |= BSP_KEY_ALL;
BSP_KEY_REN |= BSP_KEY_ALL;
#elif defined(__MSP430F5529__)
//
// Initialize keys as GPIO input pullup:
//
BSP_KEY_1_SEL &= ~(BSP_KEY_1);
BSP_KEY_1_DIR &= ~(BSP_KEY_1);
BSP_KEY_1_OUT |= BSP_KEY_1;
BSP_KEY_1_REN |= BSP_KEY_1;
BSP_KEY_2_SEL &= ~(BSP_KEY_2);
BSP_KEY_2_DIR &= ~(BSP_KEY_2);
BSP_KEY_2_OUT |= BSP_KEY_2;
BSP_KEY_2_REN |= BSP_KEY_2;
#endif
#ifndef BSP_KEY_NO_ISR
if(ui8BspKeyMode == BSP_KEY_MODE_ISR)
{
//
// Disable interrupts on key pins and clear interrupt flags
//
BSP_KEY_IE &= ~(BSP_KEY_ALL);
BSP_KEY_IFG &= ~(BSP_KEY_ALL);
//
// Connect bspKeyPushedISR() to key pins
//
ioPinIntRegister(IO_PIN_PORT_2, BSP_KEY_ALL, &bspKeyPushedISR);
//
// Set trigger type
//
ioPinIntTypeSet(IO_PIN_PORT_2, BSP_KEY_ALL, IO_PIN_RISING_EDGE);
}
#endif // BSP_KEY_NO_ISR
}
/**************************************************************************//**
* @brief Unregister an interrupt handler to the specified GPIO pin(s).
*
* @param ui32Base The GPIO port. Can be one of the following:
* \li \b IO_PIN_PORT_1
* \li \b IO_PIN_PORT_2
* @param ui8Pins The bit-packed representation of the pin(s)
*
* @return None
******************************************************************************/
void
ioPinIntUnregister(uint32_t ui32Base, uint8_t ui8Pins)
{
//
// Critical section
//
uint16_t ui16IntState = __get_interrupt_state();
__disable_interrupt();
//
// Register null function to pins
// Doing this is not necessary, but is less confusing during debug. If not
// cleared, the pins' interrupt vector tables may be non-null even when
// no custom ISR is actually registered. It is the ioPortXPinHasIsr vars
// that are used to decide whether a custom interrupt is registered or not.
//
ioPinIntRegister(ui32Base, ui8Pins, 0);
//
// Clear "pin has isr" variables
//
switch(ui32Base)
{
case IO_PIN_PORT_1:
ioPort1PinHasIsr &= ~ui8Pins;
break;
case IO_PIN_PORT_2:
ioPort2PinHasIsr &= ~ui8Pins;
break;
}
//
// End critical section
//
__set_interrupt_state(ui16IntState);
}
static void setDirection(uint8 dir){
uint8 writeByte;
//dir = 1 => RX
//dir = 0 => TX
if (dir) {
// Application specific registers
// FIFO_THR = 120
// GPIO0 = RXFIFO_THR
// GPIO2 = PKT_SYNC_RXTX
// GPIO3 = PKT_SYNC_RXTX
writeByte = INFINITE_PACKET_LENGTH_MODE;
cc112xSpiWriteReg(CC112X_PKT_CFG0, &writeByte, 1);
writeByte = 0x78; cc112xSpiWriteReg(CC112X_FIFO_CFG, &writeByte, 1);
writeByte = 0x00; cc112xSpiWriteReg(CC112X_IOCFG0, &writeByte, 1);
writeByte = 0x06; cc112xSpiWriteReg(CC112X_IOCFG2, &writeByte, 1);
writeByte = 0x06; cc112xSpiWriteReg(CC112X_IOCFG3, &writeByte, 1);
// Connect ISR function to GPIO0
ioPinIntRegister(IO_PIN_PORT_1, GPIO0, &rxFifoAboveThresholdISR);
// Interrupt on falling edge
ioPinIntTypeSet(IO_PIN_PORT_1, GPIO0, IO_PIN_RISING_EDGE);
// Clear interrupt
ioPinIntClear(IO_PIN_PORT_1, GPIO0);
// Enable interrupt
ioPinIntEnable(IO_PIN_PORT_1, GPIO0);
// Connect ISR function to GPIO2
ioPinIntRegister(IO_PIN_PORT_1, GPIO2, &syncReceivedISR);
// Interrupt on falling edge
ioPinIntTypeSet(IO_PIN_PORT_1, GPIO2, IO_PIN_RISING_EDGE);
// Clear interrupt
ioPinIntClear(IO_PIN_PORT_1, GPIO2);
// Enable interrupt
ioPinIntEnable(IO_PIN_PORT_1, GPIO2);
// Set up interrupt on GPIO3 (PKT_SYNC_RXTX)
ioPinIntRegister(IO_PIN_PORT_1, GPIO3, &packetReceivedISR);
// Interrupt on falling edge
ioPinIntTypeSet(IO_PIN_PORT_1, GPIO3, IO_PIN_FALLING_EDGE);
}
else {
// Application specific registers
// FIFO_THR = 120
// GPIO0 = TXFIFO_THR
// GPIO2 = PKT_SYNC_RXTX
writeByte = INFINITE_PACKET_LENGTH_MODE;
cc112xSpiWriteReg(CC112X_PKT_CFG0, &writeByte, 1);
writeByte = 0x78; cc112xSpiWriteReg(CC112X_FIFO_CFG, &writeByte, 1);
writeByte = 0x02; cc112xSpiWriteReg(CC112X_IOCFG0, &writeByte, 1);
writeByte = 0x06; cc112xSpiWriteReg(CC112X_IOCFG2, &writeByte, 1);
// Connect ISR function to GPIO0
ioPinIntRegister(IO_PIN_PORT_1, GPIO0, &txFifoBelowThresholdISR);
// Interrupt on falling edge
ioPinIntTypeSet(IO_PIN_PORT_1, GPIO0, IO_PIN_FALLING_EDGE);
// Clear interrupt
ioPinIntClear(IO_PIN_PORT_1, GPIO0);
// Enable interrupt
ioPinIntEnable(IO_PIN_PORT_1, GPIO0);
// Connect ISR function to GPIO2
ioPinIntRegister(IO_PIN_PORT_1, GPIO2, &packetSentISR);
// Interrupt on falling edge
ioPinIntTypeSet(IO_PIN_PORT_1, GPIO2, IO_PIN_FALLING_EDGE);
// Clear interrupt
ioPinIntClear(IO_PIN_PORT_1, GPIO2);
// Enable interrupt
ioPinIntEnable(IO_PIN_PORT_1, GPIO2);
}
}
/*******************************************************************************
* @fn runRX
*
* @brief Puts radio in RX and waits for packets. Function assumes
* that status bytes are appended in the RX_FIFO
* Update packet counter and display for each packet received.
*
* @param none
*
* @return none
*/
static void runRX(void) {
uint8 rxBuffer[128] = {0};
uint8 rxBytes;
uint8 marcState;
// Connect ISR function to GPIO2
ioPinIntRegister(IO_PIN_PORT_1, GPIO2, &radioRxISR);
// Interrupt on falling edge
ioPinIntTypeSet(IO_PIN_PORT_1, GPIO2, IO_PIN_FALLING_EDGE);
// Clear ISR flag
ioPinIntClear(IO_PIN_PORT_1, GPIO2);
// Enable interrupt
ioPinIntEnable(IO_PIN_PORT_1, GPIO2);
// Update LCD
updateLcd();
// Set radio in RX
trxSpiCmdStrobe(CC120X_SRX);
// Infinite loop
while(TRUE) {
// Wait for packet received interrupt
if(packetSemaphore == ISR_ACTION_REQUIRED) {
// Read number of bytes in RX FIFO
cc120xSpiReadReg(CC120X_NUM_RXBYTES, &rxBytes, 1);
// Check that we have bytes in FIFO
if(rxBytes != 0) {
// Read MARCSTATE to check for RX FIFO error
cc120xSpiReadReg(CC120X_MARCSTATE, &marcState, 1);
// Mask out MARCSTATE bits and check if we have a RX FIFO error
if((marcState & 0x1F) == RX_FIFO_ERROR) {
// Flush RX FIFO
trxSpiCmdStrobe(CC120X_SFRX);
} else {
// Read n bytes from RX FIFO
cc120xSpiReadRxFifo(rxBuffer, rxBytes);
// Check CRC ok (CRC_OK: bit7 in second status byte)
// This assumes status bytes are appended in RX_FIFO
// (PKT_CFG1.APPEND_STATUS = 1)
// If CRC is disabled the CRC_OK field will read 1
if(rxBuffer[rxBytes - 1] & 0x80) {
// Update packet counter
packetCounter++;
}
}
}
// Update LCD
updateLcd();
// Reset packet semaphore
packetSemaphore = ISR_IDLE;
// Set radio back in RX
trxSpiCmdStrobe(CC120X_SRX);
}
}
}
/*******************************************************************************
* @fn main
*
* @brief Runs the main routine
*
* @param none
*
* @return none
*/
void main(void) {
uint8 writeByte;
// Initialize MCU and peripherals
initMCU();
// Write radio registers (preferred settings from SmartRF Studio)
registerConfig();
// Application specific registers
// FIFO_THR = 120
// GPIO0 = RXFIFO_THR
// GPIO2 = PKT_SYNC_RXTX
// GPIO3 = PKT_SYNC_RXTX
writeByte = INFINITE_PACKET_LENGTH_MODE;
cc112xSpiWriteReg(CC112X_PKT_CFG0, &writeByte, 1);
writeByte = 0x78; cc112xSpiWriteReg(CC112X_FIFO_CFG, &writeByte, 1);
writeByte = 0x00; cc112xSpiWriteReg(CC112X_IOCFG0, &writeByte, 1);
writeByte = 0x06; cc112xSpiWriteReg(CC112X_IOCFG2, &writeByte, 1);
writeByte = 0x06; cc112xSpiWriteReg(CC112X_IOCFG3, &writeByte, 1);
bspLedSet(BSP_LED_ALL);
// Calibrate the radio according to the errata note
manualCalibration();
// Connect ISR function to GPIO0
ioPinIntRegister(IO_PIN_PORT_1, GPIO0, &rxFifoAboveThresholdISR);
// Interrupt on falling edge
ioPinIntTypeSet(IO_PIN_PORT_1, GPIO0, IO_PIN_RISING_EDGE);
// Clear interrupt
ioPinIntClear(IO_PIN_PORT_1, GPIO0);
// Enable interrupt
ioPinIntEnable(IO_PIN_PORT_1, GPIO0);
// Connect ISR function to GPIO2
ioPinIntRegister(IO_PIN_PORT_1, GPIO2, &syncReceivedISR);
// Interrupt on falling edge
ioPinIntTypeSet(IO_PIN_PORT_1, GPIO2, IO_PIN_RISING_EDGE);
// Clear interrupt
ioPinIntClear(IO_PIN_PORT_1, GPIO2);
// Enable interrupt
ioPinIntEnable(IO_PIN_PORT_1, GPIO2);
// Set up interrupt on GPIO3 (PKT_SYNC_RXTX)
ioPinIntRegister(IO_PIN_PORT_1, GPIO3, &packetReceivedISR);
// Interrupt on falling edge
ioPinIntTypeSet(IO_PIN_PORT_1, GPIO3, IO_PIN_FALLING_EDGE);
printWelcomeMessage();
while (TRUE) {
switch (state) {
//------------------------------------------------------------------
case RX_START:
//------------------------------------------------------------------
trxSpiCmdStrobe(CC112X_SRX);
pBufferIndex = rxBuffer;
// Disable interrupt on GPIO3
ioPinIntDisable(IO_PIN_PORT_1, GPIO3);
state = RX_WAIT;
//------------------------------------------------------------------
case RX_WAIT:
//------------------------------------------------------------------
if (packetReceived) {
packetReceived = FALSE;
// Check CRC and update LCD if CRC OK
if ((rxBuffer[packetLength + 3]) & CRC_OK)
updateLcd();
// Change to infinite packet length mode
pktFormat = INFINITE;
writeByte = INFINITE_PACKET_LENGTH_MODE;
cc112xSpiWriteReg(CC112X_PKT_CFG0, &writeByte, 1);
state = RX_START;
}
break;
//------------------------------------------------------------------
default:
//------------------------------------------------------------------
break;
}
}
}
