static int timer8_enable(struct timer8_priv *p)
{
iowrite16be(0xffff, p->mapbase + TCORA);
iowrite16be(0x0000, p->mapbase + _8TCNT);
iowrite16be(0x0c02, p->mapbase + _8TCR);
return 0;
}
static void timer8_set_next(struct timer8_priv *p, unsigned long delta)
{
if (delta >= 0x10000)
pr_warn("delta out of range\n");
bclr(CMIEA, p->mapbase + _8TCR);
iowrite16be(delta, p->mapbase + TCORA);
iowrite16be(0x0000, p->mapbase + _8TCNT);
bclr(CMFA, p->mapbase + _8TCSR);
bset(CMIEA, p->mapbase + _8TCR);
}
static int tpu_clocksource_enable(struct clocksource *cs)
{
struct tpu_priv *p = cs_to_priv(cs);
WARN_ON(p->cs_enabled);
iowrite16be(0, p->mapbase1 + TCNT);
iowrite16be(0, p->mapbase2 + TCNT);
iowrite8(0x0f, p->mapbase1 + TCR);
iowrite8(0x03, p->mapbase2 + TCR);
p->cs_enabled = true;
return 0;
}
static void edma_writew(struct fsl_edma_engine *edma, u16 val, void __iomem *addr)
{
if (edma->big_endian)
iowrite16be(val, addr);
else
iowrite16(val, addr);
}
static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value)
{
if (i2c->endianness == LITTLE)
iowrite16(value, i2c->base + reg);
else
iowrite16be(value, i2c->base + reg + 2);
}
static void ttl_set_value(struct gpio_chip *gpio, unsigned offset, int value)
{
struct ttl_module *mod = dev_get_drvdata(gpio->dev);
void __iomem *port;
u8 *shadow;
if (offset < 8) {
port = &mod->regs->porta;
shadow = &mod->porta_shadow;
} else if (offset < 16) {
port = &mod->regs->portb;
shadow = &mod->portb_shadow;
offset -= 8;
} else {
port = &mod->regs->portc;
shadow = &mod->portc_shadow;
offset -= 16;
}
spin_lock(&mod->lock);
if (value)
*shadow |= (1 << offset);
else
*shadow &= ~(1 << offset);
iowrite16be(*shadow, port);
spin_unlock(&mod->lock);
}
static void edma_writew(struct fsl_edma_engine *edma, u16 val, void __iomem *addr)
{
/* swap the reg offset for these in big-endian mode */
if (edma->big_endian)
iowrite16be(val, (void __iomem *)((unsigned long)addr ^ 0x2));
else
iowrite16(val, addr);
}
static int do_output(struct vmod_dev *dev,
struct vmod16a2_convert *cvrt)
{
int value = cvrt->value;
int channel = cvrt->channel;
struct vmod16a2_registers __iomem *regp =
(struct vmod16a2_registers __iomem *)dev->address;
if (channel == 0) {
iowrite16be(value, &(regp->dac0in));
iowrite16be(value, &(regp->ldac0));
} else if (channel == 1) {
iowrite16be(value, &(regp->dac1in));
iowrite16be(value, &(regp->ldac1));
} else {
printk(KERN_ERR PFX "invalid channel %d\n", channel);
return -EINVAL;
}
return 0;
}
static int do_conversion(struct file *filp,
struct vmod12e16_conversion *conversion)
{
struct vmod12e16_dev *dev = filp->private_data;
struct vmod12e16_registers __iomem *regs =
(struct vmod12e16_registers __iomem *)dev->config->address;
int channel = conversion->channel;
int ampli = conversion->amplification;
int us_elapsed;
if (down_interruptible(&dev->sem))
return -ERESTARTSYS;
/* explicitly disable interrupt mode for safely polling */
iowrite16be(VMOD_12E16_ADC_INTERRUPT_MASK, ®s->interrupt);
/* specify channel and amplification */
if ((ampli & ~((1<<2)-1)) || channel & ~((1<<4)-1)) {
up(&dev->sem);
return -EINVAL;
}
iowrite16be((ampli<<4) | channel, ®s->control);
/* wait at most the manufacturer-supplied max time */
us_elapsed = 0;
while (us_elapsed < VMOD_12E16_MAX_CONVERSION_TIME) {
udelay(VMOD_12E16_CONVERSION_TIME);
if ((ioread16be(®s->ready) & VMOD_12E16_RDY_BIT) == 0) {
conversion->data = ioread16be(®s->data) & VMOD_12E16_ADC_DATA_MASK;
udelay(VMOD_12E16_CONVERSION_TIME);
up(&dev->sem);
return 0;
}
us_elapsed += VMOD_12E16_CONVERSION_TIME;
}
/* timeout */
up(&dev->sem);
return -ETIME;
}
static void __devinit ttl_setup_device(struct ttl_module *mod)
{
/* */
iowrite16be(0x0000, &mod->regs->control);
iowrite16be(0x0001, &mod->regs->control);
iowrite16be(0x0000, &mod->regs->control);
/* */
ttl_write_reg(mod, PORTA_IOCTL, 0x00ff);
ttl_write_reg(mod, PORTB_IOCTL, 0x00ff);
ttl_write_reg(mod, PORTC_IOCTL, 0x000f);
/* */
ttl_write_reg(mod, PORTA_DIRECTION, 0x0000);
ttl_write_reg(mod, PORTB_DIRECTION, 0x0000);
ttl_write_reg(mod, PORTC_DIRECTION, 0x0000);
/* */
iowrite16be(0x0000, &mod->regs->porta);
iowrite16be(0x0000, &mod->regs->portb);
iowrite16be(0x0000, &mod->regs->portc);
/* */
ttl_write_reg(mod, MASTER_CONF_CTL, CONF_PAE | CONF_PBE | CONF_PCE);
}
static void __devinit ttl_setup_device(struct ttl_module *mod)
{
/* reset the device to a known state */
iowrite16be(0x0000, &mod->regs->control);
iowrite16be(0x0001, &mod->regs->control);
iowrite16be(0x0000, &mod->regs->control);
/* put all ports in open-drain mode */
ttl_write_reg(mod, PORTA_IOCTL, 0x00ff);
ttl_write_reg(mod, PORTB_IOCTL, 0x00ff);
ttl_write_reg(mod, PORTC_IOCTL, 0x000f);
/* set all ports as outputs */
ttl_write_reg(mod, PORTA_DIRECTION, 0x0000);
ttl_write_reg(mod, PORTB_DIRECTION, 0x0000);
ttl_write_reg(mod, PORTC_DIRECTION, 0x0000);
/* set all ports to drive zeroes */
iowrite16be(0x0000, &mod->regs->porta);
iowrite16be(0x0000, &mod->regs->portb);
iowrite16be(0x0000, &mod->regs->portc);
/* enable all ports */
ttl_write_reg(mod, MASTER_CONF_CTL, CONF_PAE | CONF_PBE | CONF_PCE);
}
static irqreturn_t timer8_interrupt(int irq, void *dev_id)
{
struct timer8_priv *p = dev_id;
if (clockevent_state_oneshot(&p->ced))
iowrite16be(0x0000, p->mapbase + _8TCR);
p->ced.event_handler(&p->ced);
bclr(CMFA, p->mapbase + _8TCSR);
return IRQ_HANDLED;
}
static int b53_mmap_write16(struct b53_device *dev, u8 page, u8 reg,
u16 value)
{
u8 __iomem *regs = dev->priv;
if (WARN_ON(reg % 2))
return -EINVAL;
if (dev->pdata && dev->pdata->big_endian)
iowrite16be(value, regs + (page << 8) + reg);
else
writew(value, regs + (page << 8) + reg);
return 0;
}
static int timer16_enable(struct clocksource *cs)
{
struct timer16_priv *p = cs_to_priv(cs);
WARN_ON(p->cs_enabled);
p->total_cycles = 0;
iowrite16be(0x0000, p->mapbase + TCNT);
iowrite8(0x83, p->mapbase + TCR);
bset(p->ovie, p->mapcommon + TISRC);
bset(p->enb, p->mapcommon + TSTR);
p->cs_enabled = true;
return 0;
}
static int raw_write(struct vmeio_device *dev, struct vmeio_riob *riob)
{
struct vme_mapping *mapx = &dev->maps[riob->mapnum-1];
int dwidth = riob->data_width ? riob->data_width : mapx->data_width;
int byte_dwidth = dwidth/8;
int bsize = riob->wsize * byte_dwidth;
int i, j, cc;
char *map, *iob;
if (bsize > vmeioMAX_BUF)
return -E2BIG;
iob = kmalloc(bsize, GFP_KERNEL);
if (!iob)
return -ENOMEM;
if ((map = mapx->kernel_va) == NULL) {
kfree(iob);
return -ENODEV;
}
cc = copy_from_user(iob, riob->buffer, bsize);
if (cc < 0) {
kfree(iob);
return -EACCES;
}
if (dev->debug > 1) {
printk("RAW:WRITE:win:%d map:0x%p ofs:0x%X amd:0x%2x dwd:%d words:%d\n",
riob->mapnum, mapx->kernel_va, riob->offset,
mapx->am, dwidth, riob->wsize);
}
for (i = 0, j = riob->offset; i < bsize; i += byte_dwidth, j += byte_dwidth) {
union vmeio_word *src = (void *)&iob[i];
if (dwidth == VME_D32)
iowrite32be(src->width4, &map[j]);
else if (dwidth == VME_D16)
iowrite16be(src->width2, &map[j]);
else if (dwidth == VME_D8)
iowrite8(src->width1, &map[j]);
else
printk(KERN_ERR PFX "invalid data width %d\n", dwidth);
}
kfree(iob);
return 0;
}
static int do_iocput(struct file *fp, struct vmod12a2_output *argp)
{
/* get lun, channel and value to output */
struct vmod_dev *dev = fp->private_data;
unsigned int channel = argp->channel;
u16 value = argp->value;
void __iomem *addr;
if (channel != 0 && channel != 1) {
printk(KERN_ERR PFX "invalid channel %d in ioctl\n", channel);
return -EINVAL;
}
/* determine channel register address and write */
addr = (void __iomem *)(dev->address + vmod12a2_offsets[channel]);
iowrite16be(value, addr);
return 0;
}
static int i2c_mux_reg_set(const struct regmux *mux, unsigned int chan_id)
{
if (!mux->data.reg)
return -EINVAL;
/*
* Write to the register, followed by a read to ensure the write is
* completed on a "posted" bus, for example PCI or write buffers.
* The endianness of reading doesn't matter and the return data
* is not used.
*/
switch (mux->data.reg_size) {
case 4:
if (mux->data.little_endian)
iowrite32(chan_id, mux->data.reg);
else
iowrite32be(chan_id, mux->data.reg);
if (!mux->data.write_only)
ioread32(mux->data.reg);
break;
case 2:
if (mux->data.little_endian)
iowrite16(chan_id, mux->data.reg);
else
iowrite16be(chan_id, mux->data.reg);
if (!mux->data.write_only)
ioread16(mux->data.reg);
break;
case 1:
iowrite8(chan_id, mux->data.reg);
if (!mux->data.write_only)
ioread8(mux->data.reg);
break;
}
return 0;
}
static void timer8_stop(struct timer8_priv *p)
{
iowrite16be(0x0000, p->mapbase + _8TCR);
}
static void oc_setreg_16be(struct ocores_i2c *i2c, int reg, u8 value)
{
iowrite16be(value, i2c->base + (reg << i2c->reg_shift));
}
static inline void mbus_write16(unsigned short b, unsigned long offset)
{
iowrite16be(b, (void *)(zion_dev.regs_base + offset));
}
static void __devinit ttl_write_reg(struct ttl_module *mod, u8 reg, u16 val)
{
iowrite16be(reg, &mod->regs->control);
iowrite16be(val, &mod->regs->control);
}
static void bgpio_write16be(void __iomem *reg, unsigned long data)
{
iowrite16be(data, reg);
}
static void fpgai2c_reg_set_16be(struct fpgalogic_i2c *i2c, int reg, u8 value)
{
iowrite16be(value, i2c->base + (reg << i2c->reg_shift));
}
static void regmap_mmio_write16be(struct regmap_mmio_context *ctx,
unsigned int reg,
unsigned int val)
{
iowrite16be(val, ctx->regs + reg);
}
