Beispiel #1
0
void up_irqinitialize(void)
{
  uint32_t regaddr;
  int i;

  /* Disable all interrupts */

  putreg32(0xffffffff, ARMV6M_NVIC_ICER);

  /* Set all interrupts (and exceptions) to the default priority */

  putreg32(DEFPRIORITY32, ARMV6M_SYSCON_SHPR2);
  putreg32(DEFPRIORITY32, ARMV6M_SYSCON_SHPR3);

  /* Now set all of the interrupt lines to the default priority */

  for (i = 0; i < 8; i++)
    {
      regaddr = ARMV6M_NVIC_IPR(i);
      putreg32(DEFPRIORITY32, regaddr);
    }

  /* currents_regs is non-NULL only while processing an interrupt */

  current_regs = NULL;

  /* Attach the SVCall and Hard Fault exception handlers.  The SVCall
   * exception is used for performing context switches; The Hard Fault
   * must also be caught because a SVCall may show up as a Hard Fault
   * under certain conditions.
   */

  irq_attach(NUC_IRQ_SVCALL, up_svcall);
  irq_attach(NUC_IRQ_HARDFAULT, up_hardfault);

  /* Attach all other processor exceptions (except reset and sys tick) */

#ifdef CONFIG_DEBUG
  irq_attach(NUC_IRQ_NMI, nuc_nmi);
  irq_attach(NUC_IRQ_PENDSV, nuc_pendsv);
  irq_attach(NUC_IRQ_RESERVED, nuc_reserved);
#endif

  nuc_dumpnvic("initial", NR_IRQS);

#ifndef CONFIG_SUPPRESS_INTERRUPTS

  /* And finally, enable interrupts */

  irqenable();
#endif
}
void up_timer_initialize(void)
{
  uint32_t regval;

  /* Set the SysTick interrupt to the default priority */

  regval = getreg32(ARMV6M_SYSCON_SHPR3);
  regval &= ~SYSCON_SHPR3_PRI_15_MASK;
  regval |= (NVIC_SYSH_PRIORITY_DEFAULT << SYSCON_SHPR3_PRI_15_SHIFT);
  putreg32(regval, ARMV6M_SYSCON_SHPR3);

  /* Configure SysTick to interrupt at the requested rate */

  putreg32(SYSTICK_RELOAD, ARMV6M_SYSTICK_RVR);

  /* Attach the timer interrupt vector */

  (void)irq_attach(SAM_IRQ_SYSTICK, (xcpt_t)up_timerisr);

  /* Enable SysTick interrupts */

  putreg32((SYSTICK_CSR_TICKINT | SYSTICK_CSR_ENABLE), ARMV6M_SYSTICK_CSR);

  /* And enable the timer interrupt */

  up_enable_irq(SAM_IRQ_SYSTICK);
}
xcpt_t up_irqbutton(int id, xcpt_t irqhandler)
{
  xcpt_t oldhandler = NULL;

  if (id < BOARD_NBUTTONS)
    {
      irqstate_t flags;

      /* Disable interrupts until we are done.  This guarantees that the
       * following operations are atomic.
       */

      flags = irqsave();

      /* Get the old button interrupt handler and save the new one */

      oldhandler      = g_irqbutton[id];
      g_irqbutton[id] = irqhandler;

      /* Configure the interrupt */

      a1x_pioirq(xxx);
      (void)irq_attach(xxx, irqhandler);
      a1x_pioirqenable(xxx);
      irqrestore(flags);
    }

  /* Return the old button handler (so that it can be restored) */

  return oldhandler;
}
Beispiel #4
0
void up_dmainitialize(void)
{
  int i;

  for (i = 0; i < DMA_CHANNEL_NUM; i++)
    {
      g_dma.phydmach[i].inprogress = 0;
      sq_init(&g_dma.phydmach[i].req_q);
    }

  nxsem_init(&g_dma.exclsem, 0, 1);

  if (irq_attach(LC823450_IRQ_DMAC, dma_interrupt, NULL) != 0)
    {
      return;
    }
  up_enable_irq(LC823450_IRQ_DMAC);

  /* Clock & Reset */

  modifyreg32(MCLKCNTBASIC, 0, MCLKCNTBASIC_DMAC_CLKEN);
  modifyreg32(MRSTCNTBASIC, 0, MRSTCNTBASIC_DMAC_RSTB);

  /* DMAC enable */

  modifyreg32(DMACCONFIG, 0, DMACCONFIG_EN);

#ifdef DMA_TEST
  lc823450_dma_test();
#endif

  /* clock disable */

  modifyreg32(MCLKCNTBASIC, MCLKCNTBASIC_DMAC_CLKEN, 0);
}
Beispiel #5
0
void misoc_timer_initialize(void)
{
  /* Clear event pending */

  timer0_ev_pending_write(timer0_ev_pending_read());

  /* Disable timer*/

  timer0_en_write(0);

  /* Setup the timer reload register to generate interrupts at the rate of
   * CLOCKS_PER_SEC.
   */

  timer0_reload_write(SYSTICK_RELOAD);
  timer0_load_write(SYSTICK_RELOAD);

  /* Enable timer */

  timer0_en_write(1);

  /* Attach the timer interrupt vector */

  (void)irq_attach(TIMER0_INTERRUPT, up_timerisr);

  /* And enable the timer interrupt */

  up_enable_irq(TIMER0_INTERRUPT);

  /* Enable IRQ of the timer core */

  timer0_ev_enable_write(1);
}
Beispiel #6
0
void arm_timer_initialize(void)
{
  uint32_t regval;

  /* Configure SysTick to interrupt at the requested rate */

  putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD);
  putreg32(0, NVIC_SYSTICK_CURRENT);

  /* Attach the timer interrupt vector */

  (void)irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr, NULL);

  /* Enable SysTick interrupts:
   *
   *   NVIC_SYSTICK_CTRL_CLKSOURCE=0 : Use the implementation defined clock
   *                                   source which, for the STM32F7, will be
   *                                   HCLK/8
   *   NVIC_SYSTICK_CTRL_TICKINT=1   : Generate interrupts
   *   NVIC_SYSTICK_CTRL_ENABLE      : Enable the counter
   */

  regval = (NVIC_SYSTICK_CTRL_TICKINT | NVIC_SYSTICK_CTRL_ENABLE);
  putreg32(regval, NVIC_SYSTICK_CTRL);

  /* And enable the timer interrupt */

  up_enable_irq(STM32_IRQ_SYSTICK);
}
Beispiel #7
0
void
interface_init(void)
{
	pc_txns = perf_alloc(PC_ELAPSED, "txns");
	pc_errors = perf_alloc(PC_COUNT, "errors");
	pc_ore = perf_alloc(PC_COUNT, "overrun");
	pc_fe = perf_alloc(PC_COUNT, "framing");
	pc_ne = perf_alloc(PC_COUNT, "noise");
	pc_idle = perf_alloc(PC_COUNT, "idle");
	pc_badidle = perf_alloc(PC_COUNT, "badidle");
	pc_regerr = perf_alloc(PC_COUNT, "regerr");
	pc_crcerr = perf_alloc(PC_COUNT, "crcerr");

	/* allocate DMA */
	tx_dma = stm32_dmachannel(PX4FMU_SERIAL_TX_DMA);
	rx_dma = stm32_dmachannel(PX4FMU_SERIAL_RX_DMA);

	/* configure pins for serial use */
	stm32_configgpio(PX4FMU_SERIAL_TX_GPIO);
	stm32_configgpio(PX4FMU_SERIAL_RX_GPIO);

	/* reset and configure the UART */
	rCR1 = 0;
	rCR2 = 0;
	rCR3 = 0;

	/* clear status/errors */
	(void)rSR;
	(void)rDR;

	/* configure line speed */
	uint32_t usartdiv32 = PX4FMU_SERIAL_CLOCK / (PX4FMU_SERIAL_BITRATE / 2);
	uint32_t mantissa = usartdiv32 >> 5;
	uint32_t fraction = (usartdiv32 - (mantissa << 5) + 1) >> 1;
	rBRR = (mantissa << USART_BRR_MANT_SHIFT) | (fraction << USART_BRR_FRAC_SHIFT);

	/* connect our interrupt */
	irq_attach(PX4FMU_SERIAL_VECTOR, serial_interrupt);
	up_enable_irq(PX4FMU_SERIAL_VECTOR);

	/* enable UART and error/idle interrupts */
	rCR3 = USART_CR3_EIE;
	rCR1 = USART_CR1_RE | USART_CR1_TE | USART_CR1_UE | USART_CR1_IDLEIE;

#if 0	/* keep this for signal integrity testing */
	for (;;) {
		while (!(rSR & USART_SR_TXE))
			;
		rDR = 0xfa;
		while (!(rSR & USART_SR_TXE))
			;
		rDR = 0xa0;
	}
#endif

	/* configure RX DMA and return to listening state */
	dma_reset();

	debug("serial init");
}
Beispiel #8
0
static int at91_pin_init(void) {
	REG_STORE(AT91C_PMC_PCER, 1L << AT91C_ID_PIOA);
	// TODO check return value.
	irq_attach(AT91C_ID_PIOA, irq_pin_handler, 0, NULL, "AT91 PIO pins");
	pin_get_input_changed();
	return 0;
}
Beispiel #9
0
static int stm32_rnginitialize()
{
  uint32_t regval;

  vdbg("Initializing RNG\n");

  memset(&g_rngdev, 0, sizeof(struct rng_dev_s));

  sem_init(&g_rngdev.rd_devsem, 0, 1);

  if (irq_attach(STM32_IRQ_RNG, stm32_interrupt))
    {
      /* We could not attach the ISR to the interrupt */

      vdbg("Could not attach IRQ.\n");

      return -EAGAIN;
    }

  /* Enable interrupts */

  regval = getreg32(STM32_RNG_CR);
  regval |=  RNG_CR_IE;
  putreg32(regval, STM32_RNG_CR);

  up_enable_irq(STM32_IRQ_RNG);

  return OK;
}
Beispiel #10
0
static int mipsnet_init(void) {
	struct net_device *netdev;
	int err;
	struct mipsnet_regs *regs;

	netdev = etherdev_alloc(0);
	if (!netdev) {
		return -ENOMEM;
	}

	/*
	 * TODO: probe for these or load them from PARAM
	 */
	netdev->base_addr = BASE_ADDR;
	netdev->irq = IRQ_NUM;
	netdev->drv_ops = &mipsnet_drv_ops;

	err = irq_attach(IRQ_NUM, mipsnet_interrupt_handler, 0, netdev, "mipsnet");
	if (err) {
		return err;
	}

	regs = (struct mipsnet_regs *)netdev->base_addr;
	out32(MIPSNET_INTCTL_TESTBIT, &regs->interruptControl);

	return inetdev_register_dev(netdev);
}
Beispiel #11
0
static int tsc_attach(FAR struct ads7843e_config_s *state, xcpt_t isr)
{
    /* Attach the XPT2046 interrupt */

    ivdbg("Attaching %p to IRQ %d\n", isr, SAM_TSC_IRQ);
    return irq_attach(SAM_TSC_IRQ, isr);
}
Beispiel #12
0
xcpt_t sam_setup_overcurrent(xcpt_t handler)
{
#if defined(CONFIG_SAMA5_PIOD_IRQ) && (defined(CONFIG_SAMA5_UHPHS_RHPORT2) || \
    defined(CONFIG_SAMA5_UHPHS_RHPORT3))

  xcpt_t oldhandler;
  irqstate_t flags;

  /* Disable interrupts until we are done.  This guarantees that the
   * following operations are atomic.
   */

  flags = enter_critical_section();

  /* Get the old interrupt handler and save the new one */

  oldhandler  = g_ochandler;
  g_ochandler = handler;

  /* Configure the interrupt */

  sam_pioirq(PIO_USBBC_VBUS_OVERCURRENT);
  (void)irq_attach(IRQ_USBBC_VBUS_OVERCURRENT, handler);
  sam_pioirqenable(IRQ_USBBC_VBUS_OVERCURRENT);

  /* Return the old handler (so that it can be restored) */

  leave_critical_section(flags);
  return oldhandler;

#else
  return NULL;

#endif
}
int
up_pwm_input_init(uint32_t channel_mask)
{
	memset(&rc_in, 0, sizeof(rc_in));
	rc_in.input_source = RC_INPUT_SOURCE_VRBRAIN_PWM;

	/* attach interrupt for the timers */
	for (unsigned i = 0; i < PWM_INPUT_MAX_TIMERS; i++) {
		if (pwm_input_timers[i].base != 0)
			irq_attach(pwm_input_timers[i].vector, pwm_input_timer_isr);
	}

	/* do basic timer initialisation first */
	for (unsigned i = 0; i < PWM_INPUT_MAX_TIMERS; i++) {
		if (pwm_input_timers[i].base != 0)
			pwm_input_timer_init(i);
	}

	/* now init channels */
	for (unsigned i = 0; i < PWM_INPUT_MAX_CHANNELS; i++) {
		/* don't do init for disabled channels; this leaves the pin configs alone */
		if (((1 << i) & channel_mask) && (pwm_input_channels[i].timer_channel != 0))
			pwm_input_channel_init(i);
	}

	/* enable IRQs of timers */
	for (unsigned i = 0; i < PWM_INPUT_MAX_TIMERS; i++) {
		if (pwm_input_timers[i].base != 0)
			up_enable_irq(pwm_input_timers[i].vector);
	}

	return OK;
}
Beispiel #14
0
/*
 * Initialise the timer we are going to use.
 */
void PWMIN::_timer_init(void)
{
	/* run with interrupts disabled in case the timer is already
	 * setup. We don't want it firing while we are doing the setup */
	irqstate_t flags = px4_enter_critical_section();

	/* configure input pin */
	px4_arch_configgpio(GPIO_PWM_IN);

	// XXX refactor this out of this driver
	/* configure reset pin */
	px4_arch_configgpio(GPIO_VDD_RANGEFINDER_EN);

	/* claim our interrupt vector */
	irq_attach(PWMIN_TIMER_VECTOR, pwmin_tim_isr, NULL);

	/* Clear no bits, set timer enable bit.*/
	modifyreg32(PWMIN_TIMER_POWER_REG, 0, PWMIN_TIMER_POWER_BIT);

	/* disable and configure the timer */
	rCR1 = 0;
	rCR2 = 0;
	rSMCR = 0;
	rDIER = DIER_PWMIN_A;
	rCCER = 0;		/* unlock CCMR* registers */
	rCCMR1 = CCMR1_PWMIN;
	rCCMR2 = CCMR2_PWMIN;
	rSMCR = SMCR_PWMIN_1;	/* Set up mode */
	rSMCR = SMCR_PWMIN_2;	/* Enable slave mode controller */
	rCCER = CCER_PWMIN;
	rDCR = 0;

	/* for simplicity scale by the clock in MHz. This gives us
	 * readings in microseconds which is typically what is needed
	 * for a PWM input driver */
	uint32_t prescaler = PWMIN_TIMER_CLOCK / 1000000UL;

	/*
	 * define the clock speed. We want the highest possible clock
	 * speed that avoids overflows.
	 */
	rPSC = prescaler - 1;

	/* run the full span of the counter. All timers can handle
	 * uint16 */
	rARR = UINT16_MAX;

	/* generate an update event; reloads the counter, all registers */
	rEGR = GTIM_EGR_UG;

	/* enable the timer */
	rCR1 = GTIM_CR1_CEN;

	/* enable interrupts */
	up_enable_irq(PWMIN_TIMER_VECTOR);

	px4_leave_critical_section(flags);

	_timer_started = true;
}
Beispiel #15
0
void up_timerinit(void)
{
  /* Configure and enable TIMER1.  Used the computed TCKPS divider and timer
   * match valude.  The source will be either the internal PBCLOCK (TCS=0) or
   * the external SOSC (TCS=1)
   */

  putreg32((TIMER1_CON_TCKPS|TIMER1_CON_TCS), PIC32MX_TIMER1_CON);
  putreg32(0, PIC32MX_TIMER1_CNT);
  putreg32(TIMER1_MATCH-1, PIC32MX_TIMER1_PR);
  putreg32(TIMER_CON_ON, PIC32MX_TIMER1_CONSET);

  /* Configure the timer interrupt */

  up_clrpend_irq(PIC32MX_IRQSRC_T1);
  (void)up_prioritize_irq(PIC32MX_IRQ_T1, CONFIG_PIC32MX_T1PRIO);

  /* Attach the timer interrupt vector */

  (void)irq_attach(PIC32MX_IRQ_T1, (xcpt_t)up_timerisr);

  /* And enable the timer interrupt */

  up_enable_irq(PIC32MX_IRQSRC_T1);
}
Beispiel #16
0
int str71x_xtiinitialize(void)
{
  int ret;

  /* Mask all interrupts by setting XTI MRH/L to zero */

  putreg8(0, STR71X_XTI_MRH);
  putreg8(0, STR71X_XTI_MRL);

  /* Clear any pending interrupts by setting XTI PRH/L to zero */

  putreg8(0, STR71X_XTI_PRH);
  putreg8(0, STR71X_XTI_PRL);

  /* Attach the XTI interrupt */

  ret = irq_attach(STR71X_IRQ_XTI, str71x_xtiinterrupt);
  if (ret == OK)
    {
      /* Enable the XTI interrupt at the XTI */

      putreg8(STR71X_XTICTRL_ID1S, STR71X_XTI_CTRL);

      /* And enable the XTI interrupt at the interrupt controller */

      up_enable_irq(STR71X_IRQ_XTI);
    }
  return ret;
}
Beispiel #17
0
void arm_timer_initialize(void)
{
  uint32_t regval;

  /* Set the SysTick interrupt to the default priority */

  regval  = getreg32(NVIC_SYSH12_15_PRIORITY);
  regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK;
  regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT);
  putreg32(regval, NVIC_SYSH12_15_PRIORITY);

  /* Configure SysTick to interrupt at the requested rate */

  putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD);
  putreg32(0, NVIC_SYSTICK_CURRENT);

  /* Attach the timer interrupt vector */

  (void)irq_attach(SAM_IRQ_SYSTICK, (xcpt_t)sam_timerisr, NULL);

  /* Enable SysTick interrupts using the processor clock source. */

  putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT |
            NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL);

  /* And enable the timer interrupt */

  up_enable_irq(SAM_IRQ_SYSTICK);
}
Beispiel #18
0
int up_rtc_initialize(void)
{
  int ret;

  rtc_dumpregs("On reset");

  /* Attach the RTC interrupt handler */

#ifdef CONFIG_RTC_ALARM
  ret = irq_attach(LPC17_IRQ_RTC, rtc_interrupt);
  if (ret == OK)
    {
      up_enable_irq(LPC17_IRQ_RTC);
    }
#endif /* CONFIG_RTC_ALARM */

  /* Perform the one-time setup of the RTC */

  ret = rtc_setup();

  /* Configure RTC interrupt to catch alarm interrupts. All RTC interrupts are
   * connected to the EXTI controller.  To enable the RTC Alarm interrupt, the
   * following sequence is required:
   *
   * 1. Configure and enable the EXTI Line 17 in interrupt mode and select the
   *    rising edge sensitivity.
   * 2. Configure and enable the RTC_Alarm IRQ channel in the NVIC.
   * 3. Configure the RTC to generate RTC alarms (Alarm A or Alarm B).
   */

  g_rtc_enabled = true;
  rtc_dumpregs("After Initialization");
  return OK;
}
Beispiel #19
0
static void ssp_cdirqsetup(int irq, xcpt_t irqhandler)
{
  irqstate_t flags;

  /* Disable interrupts until we are done */

  flags = irqsave();

  /* Configure the interrupt.  Either attach and enable the new
   * interrupt or disable and detach the old interrupt handler.
   */

  if (irqhandler)
    {
      /* Attach then enable the new interrupt handler */

      (void)irq_attach(irq, irqhandler);
      up_enable_irq(irq);
    }
  else
    {
      /* Disable then detach the old interrupt handler */

      up_disable_irq(irq);
      (void)irq_detach(irq);
    }
}
Beispiel #20
0
static int btm_bluetooth_init(void) {
	irq_attach(OPTION_GET(NUMBER,irq_num), btm_bt_us_handler, 0, NULL, "bt reader");
	// TODO error handling?

	init_usart();
	return 0;
}
void up_timer_initialize(void)
{
  uint32_t regval;

  /* Set the SysTick interrupt to the default priority */

  regval = getreg32(ARMV6M_SYSCON_SHPR3);
  regval &= ~SYSCON_SHPR3_PRI_15_MASK;
  regval |= (NVIC_SYSH_PRIORITY_DEFAULT << SYSCON_SHPR3_PRI_15_SHIFT);
  putreg32(regval, ARMV6M_SYSCON_SHPR3);

  /* Configure SysTick to interrupt at the requested rate */

  putreg32(SYSTICK_RELOAD, ARMV6M_SYSTICK_RVR);

  /* Attach the timer interrupt vector */

  (void)irq_attach(KL_IRQ_SYSTICK, (xcpt_t)up_timerisr);

  /* Enable SysTick interrupts.  "The CLKSOURCE bit in SysTick Control and
   * Status register selects either the core clock (when CLKSOURCE = 1) or
   * a divide-by-16 of the core clock (when CLKSOURCE = 0). ..."
   */

#ifdef CONFIG_KL_SYSTICK_CORECLK
  putreg32((SYSTICK_CSR_CLKSOURCE | SYSTICK_CSR_TICKINT | SYSTICK_CSR_ENABLE),
           ARMV6M_SYSTICK_CSR);
#else
  putreg32((SYSTICK_CSR_TICKINT | SYSTICK_CSR_ENABLE), ARMV6M_SYSTICK_CSR);
#endif

  /* And enable the timer interrupt */

  up_enable_irq(KL_IRQ_SYSTICK);
}
Beispiel #22
0
xcpt_t up_irqbutton(int id, xcpt_t irqhandler)
{
  xcpt_t oldhandler = NULL;

  if (id == BUTTON_USER1)
    {
      irqstate_t flags;

      /* Disable interrupts until we are done.  This guarantees that the
       * following operations are atomic.
       */

      flags = irqsave();

      /* Get the old button interrupt handler and save the new one */

      oldhandler = *g_irquser1;
      *g_irquser1 = irqhandler;

      /* Configure the interrupt */

      sam_pioirq(IRQ_USER1);
      (void)irq_attach(IRQ_USER1, irqhandler);
      sam_pioirqenable(IRQ_USER1);
    }

  /* Return the old button handler (so that it can be restored) */

  return oldhandler;
}
Beispiel #23
0
static xcpt_t up_irqbuttonx(int irq, xcpt_t irqhandler, xcpt_t *store)
{
  xcpt_t oldhandler;
  irqstate_t flags;

  /* Disable interrupts until we are done.  This guarantees that the following
   * operations are atomic.
   */

  flags = irqsave();

  /* Get the old button interrupt handler and save the new one */

  oldhandler = *store;
  *store = irqhandler;

  /* Configure the interrupt */

  sam3u_gpioirq(irq);
  (void)irq_attach(irq, irqhandler);
  sam3u_gpioirqenable(irq);
  irqrestore(flags);

  /* Return the old button handler (so that it can be restored) */

  return oldhandler;
}
Beispiel #24
0
static int tsc_attach(FAR struct ads7843e_config_s *state, xcpt_t isr)
{
  /* Attach the ADS7843E interrupt */

  iinfo("Attaching %p to IRQ %d\n", isr, SAM_TCS_IRQ);
  return irq_attach(SAM_TCS_IRQ, isr, NULL);
}
Beispiel #25
0
int up_wdtinit(void)
{
  int ret;

  dbg("C547x Watchdog Driver\n");

  /* Register as /dev/wdt */

  ret = register_driver("/dev/wdt", &g_wdtops, 0666, NULL);
  if (ret)
    {
      return ERROR;
    }

  /* Register for an interrupt level callback through wdt_interrupt */

  dbg("Attach to IRQ=%d\n", C5471_IRQ_WATCHDOG);

  /* Make sure that the timer is stopped */

  c5471_wdt_cntl = C5471_TIMER_STOP;

  /* Request the interrupt. */

  ret = irq_attach(C5471_IRQ_WATCHDOG, wdt_interrupt);
  if (ret)
    {
      unregister_driver("/dev/wdt");
      return ERROR;
    }

  return OK;
}
Beispiel #26
0
xcpt_t board_button_irq(int id, xcpt_t irqhandler)
{
  xcpt_t oldhandler = NULL;

  if (id == BUTTON_SW0)
    {
      irqstate_t flags;

      /* Disable interrupts until we are done.  This guarantees that the
       * following operations are atomic.
       */

      flags = irqsave();

      /* Get the old button interrupt handler and save the new one */

      oldhandler = *g_irqsw0;
      *g_irqsw0 = irqhandler;

      /* Configure the interrupt */

      sam_portirq(IRQ_SW0);
      (void)irq_attach(IRQ_SW0, irqhandler);
      sam_portirqenable(IRQ_SW0);
      irqrestore(flags);
    }

  /* Return the old button handler (so that it can be restored) */

  return oldhandler;
}
Beispiel #27
0
/* Initialize the hardware module lirc_rpi */
int module_init(void) {
#ifdef USE_LIRC
	if(initialized == 0) {
		if(!hw.init_func()) {
			exit(EXIT_FAILURE);
		}

		/* Only set the frequency once */
		if(setfreq == 0) {
			freq = FREQ433;
			/* Set the lirc_rpi frequency to 433.92Mhz */
			if(hw.ioctl_func(LIRC_SET_SEND_CARRIER, &freq) == -1) {
				logprintf(LOG_ERR, "could not set lirc_rpi send frequency");
				exit(EXIT_FAILURE);
			}
			setfreq = 1;
		}
		logprintf(LOG_DEBUG, "initialized lirc_rpi module");
		initialized = 1;
	
	}
#else
	if(gpio_request(GPIO_IN_PIN) == 0) {
		/* Attach an interrupt to the requested pin */
		irq_attach(GPIO_IN_PIN, CHANGE);
	} else {
		return EXIT_FAILURE;		
	}
#endif
	return EXIT_SUCCESS;
}
Beispiel #28
0
void up_timer_initialize(void)
{
  uint32_t regval;

  /* Set the SysTick interrupt to the default priority */

  regval = getreg32(NVIC_SYSH12_15_PRIORITY);
  regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK;
  regval |= (LPC43M4_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT);
  putreg32(regval, NVIC_SYSH12_15_PRIORITY);

  /* Make sure that the SYSTICK clock source is set to use the LPC43xx CCLK */

  regval = getreg32(NVIC_SYSTICK_CTRL);
  regval |= NVIC_SYSTICK_CTRL_CLKSOURCE;
  putreg32(regval, NVIC_SYSTICK_CTRL);

  /* Configure SysTick to interrupt at the requested rate */

  putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD);

  /* Attach the timer interrupt vector */

  (void)irq_attach(LPC43_IRQ_SYSTICK, (xcpt_t)up_timerisr);

  /* Enable SysTick interrupts */

  putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE|NVIC_SYSTICK_CTRL_TICKINT|
            NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL);

  /* And enable the timer interrupt */

  up_enable_irq(LPC43_IRQ_SYSTICK);
}
Beispiel #29
0
static int metal_cntr_irq_attach(struct metal_irq_controller *cntr,
				 int irq, metal_irq_handler hd, void *arg)
{
	if (irq < 0 || irq >= cntr->irq_num)
		return -EINVAL;

	if (hd) {
		struct metal_irq *data;

		data = metal_allocate_memory(sizeof(*data));
		if (data == NULL)
			return -ENOMEM;

		data->hd  = hd;
		data->arg = arg;

		irq_attach(irq, metal_cntr_irq_handler, data);
	} else {
		unsigned int flags;

		flags = metal_irq_save_disable();
		irq_dispatch(irq, NULL); /* fake a irq request */
		metal_irq_restore_enable(flags);
	}

	return 0;
}
Beispiel #30
0
void z80_timer_initialize(void)
{
  uint16_t reload;

  /* Disable the timer */

  outp(EZ80_TMR0_CTL, 0x00);

  /* Attach system timer interrupts */

  irq_attach(EZ80_IRQ_SYSTIMER, (xcpt_t)ez80_timerisr, NULL);

  /* Set up the timer reload value */
  /* Write to the timer reload register to set the reload value.
   *
   * In continuous mode:
   *
   *   timer_period = reload_value x clock_divider / system_clock_frequency
   * or
   *   reload_value = (timer_period * system_clock_frequency) / clock_divider
   *
   * For timer_period=10mS, and clock_divider=16, that would yield:
   *
   *   reload_value = system_clock_frequency / 1600
   *
   * For a system timer of 50,000,000 that would result in a reload value of
   * 31,250
   *
   * NOTE: The system clock frequency value is defined in the board.h file
   */

  reload = (uint16_t)(ez80_systemclock / 1600);
  outp(EZ80_TMR0_RRH, (uint8_t)(reload >> 8));
  outp(EZ80_TMR0_RRL, (uint8_t)(reload));

  /* Clear any pending timer interrupts */

#if defined(_EZ80F91)
  (void)inp(EZ80_TMR0_IIR);
#elif defined(_EZ80L92) || defined(_EZ80F92) ||defined(_EZ80F93)
  (void)inp(EZ80_TMR0_CTL);
#endif

  /* Configure and enable the timer */

#if defined(_EZ80190)
  outp(EZ80_TMR0_CTL, 0x5f);
#elif defined(_EZ80F91)
  outp(EZ80_TMR0_CTL, (EZ80_TMRCLKDIV_16|EZ80_TMRCTL_TIMCONT|EZ80_TMRCTL_RLD|EZ80_TMRCTL_TIMEN));
#elif defined(_EZ80L92) || defined(_EZ80F92) ||defined(_EZ80F93)
  outp(EZ80_TMR0_CTL, 0x57);
#endif

/* Enable timer end-of-count interrupts */

#if defined(_EZ80F91)
  outp(EZ80_TMR0_IER, EZ80_TMRIER_EOCEN);
#endif
}