/* Given an index into the irq table, return the interrupt's current priority */
static INT8 dsp56k_get_irq_priority(dsp56k_core* cpustate, int index)
{
// 1-12
switch (index)
{
// Non-maskable
case 0: return 3; // Hardware RESET
case 1: return 3; // Illegal Instruction
case 2: return 3; // Stack Error
case 3: return 3; // Reserved
case 4: return 3; // SWI
// Poll the IPR for these guys.
case 5: return irqa_ipl(cpustate); // IRQA
case 6: return irqb_ipl(cpustate); // IRQB
case 7: return -1; // Reserved
case 8: return ssi0_ipl(cpustate); // SSI0 Receive Data with Exception
case 9: return ssi0_ipl(cpustate); // SSI0 Receive Data
case 10: return ssi0_ipl(cpustate); // SSI0 Transmit Data with Exception
case 11: return ssi0_ipl(cpustate); // SSI0 Transmit Data
case 12: return ssi1_ipl(cpustate); // SSI1 Receive Data with Exception
case 13: return ssi1_ipl(cpustate); // SSI1 Receive Data
case 14: return ssi1_ipl(cpustate); // SSI1 Transmit Data with Exception
case 15: return ssi1_ipl(cpustate); // SSI1 Transmit Data
case 16: return tm_ipl(cpustate); // Timer Overflow
case 17: return tm_ipl(cpustate); // Timer Compare
case 18: return host_ipl(cpustate); // Host DMA Receive Data
case 19: return host_ipl(cpustate); // Host DMA Transmit Data
case 20: return host_ipl(cpustate); // Host Receive Data
case 21: return host_ipl(cpustate); // Host Transmit Data
case 22: return host_ipl(cpustate); // Host Command 0 (Default)
case 23: return codec_ipl(cpustate); // Codec Receive/Transmit
case 24: return host_ipl(cpustate); // Host Command 1 // TODO: Are all host ipl's the same?
case 25: return host_ipl(cpustate); // Host Command 2
case 26: return host_ipl(cpustate); // Host Command 3
case 27: return host_ipl(cpustate); // Host Command 4
case 28: return host_ipl(cpustate); // Host Command 5
case 29: return host_ipl(cpustate); // Host Command 6
case 30: return host_ipl(cpustate); // Host Command 7
case 31: return host_ipl(cpustate); // Host Command 8
default: break;
}
return -1;
}
/* Given an index into the irq table, return the interrupt's current priority */
INT8 dsp56k_get_irq_priority(dsp56k_core* cpustate, int index)
{
/* 1-12 */
switch (index)
{
/* Non-maskable */
case 0: return 3; /* Hardware RESET */
case 1: return 3; /* Illegal Instruction */
case 2: return 3; /* Stack Error */
case 3: return 3; /* Reserved */
case 4: return 3; /* SWI */
/* Poll the IPR for these guys. */
case 5: return irqa_ipl(cpustate); /* IRQA */
case 6: return irqb_ipl(cpustate); /* IRQB */
case 7: return -1; /* Reserved */
case 8: return ssi0_ipl(cpustate); /* SSI0 Receive Data with Exception */
case 9: return ssi0_ipl(cpustate); /* SSI0 Receive Data */
case 10: return ssi0_ipl(cpustate); /* SSI0 Transmit Data with Exception */
case 11: return ssi0_ipl(cpustate); /* SSI0 Transmit Data */
case 12: return ssi1_ipl(cpustate); /* SSI1 Receive Data with Exception */
case 13: return ssi1_ipl(cpustate); /* SSI1 Receive Data */
case 14: return ssi1_ipl(cpustate); /* SSI1 Transmit Data with Exception */
case 15: return ssi1_ipl(cpustate); /* SSI1 Transmit Data */
case 16: return tm_ipl(cpustate); /* Timer Overflow */
case 17: return tm_ipl(cpustate); /* Timer Compare */
case 18: return host_ipl(cpustate); /* Host DMA Receive Data */
case 19: return host_ipl(cpustate); /* Host DMA Transmit Data */
case 20: return host_ipl(cpustate); /* Host Receive Data */
case 21: return host_ipl(cpustate); /* Host Transmit Data */
case 22: return host_ipl(cpustate); /* Host Command 0 (Default) */
case 23: return codec_ipl(cpustate); /* Codec Receive/Transmit */
case 24: return host_ipl(cpustate); /* Host Command 1 // TODO: Are all host ipl's the same? */
case 25: return host_ipl(cpustate); /* Host Command 2 */
case 26: return host_ipl(cpustate); /* Host Command 3 */
case 27: return host_ipl(cpustate); /* Host Command 4 */
case 28: return host_ipl(cpustate); /* Host Command 5 */
case 29: return host_ipl(cpustate); /* Host Command 6 */
case 30: return host_ipl(cpustate); /* Host Command 7 */
case 31: return host_ipl(cpustate); /* Host Command 8 */
default: break;
}
return -1;
}
