static void __init imx6q_init_irq(void) { l2x0_of_init(0, ~0UL); imx_src_init(); imx_gpc_init(); irqchip_init(); }
void __init bcm2708_init_irq(void) { if (of_have_populated_dt()) irqchip_init(); else armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0); }
/* * FIXME: Should we set up the GPIO domain here? * * The problem is that we cannot put the interrupt resources into the platform * device until the irqdomain has been added. Right now, we set the GIC interrupt * domain from init_irq(), then load the gpio driver from * core_initcall(nmk_gpio_init) and add the platform devices from * arch_initcall(customize_machine). * * This feels fragile because it depends on the gpio device getting probed * _before_ any device uses the gpio interrupts. */ void __init ux500_init_irq(void) { gic_arch_extn.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND; irqchip_init(); /* * Init clocks here so that they are available for system timer * initialization. */ if (cpu_is_u8500_family()) { prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1); ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1); u8500_of_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE, U8500_CLKRST3_BASE, U8500_CLKRST5_BASE, U8500_CLKRST6_BASE); } else if (cpu_is_u9540()) { prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1); ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1); u9540_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE, U8500_CLKRST3_BASE, U8500_CLKRST5_BASE, U8500_CLKRST6_BASE); } else if (cpu_is_u8540()) { prcmu_early_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1); ux500_pm_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1); u8540_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE, U8500_CLKRST3_BASE, U8500_CLKRST5_BASE, U8500_CLKRST6_BASE); } }
void __init init_IRQ(void) { if (IS_ENABLED(CONFIG_OF) && !machine_desc->init_irq) irqchip_init(); else machine_desc->init_irq(); }
/* IRQ for DMA channels */ DEFINE_RES_NAMED(gic_iid(0x7b), 5, NULL, IORESOURCE_IRQ), }; static void __init r8a7778_register_hpb_dmae(void) { platform_device_register_resndata(NULL, "hpb-dma-engine", -1, hpb_dmae_resources, ARRAY_SIZE(hpb_dmae_resources), &dma_platform_data, sizeof(dma_platform_data)); } void __init r8a7778_add_standard_devices(void) { r8a7778_add_dt_devices(); r8a7778_register_tmu(0); r8a7778_register_scif(0); r8a7778_register_scif(1); r8a7778_register_scif(2); r8a7778_register_scif(3); r8a7778_register_scif(4); r8a7778_register_scif(5); r8a7778_register_i2c(0); r8a7778_register_i2c(1); r8a7778_register_i2c(2); r8a7778_register_i2c(3); r8a7778_register_hspi(0); r8a7778_register_hspi(1); r8a7778_register_hspi(2); r8a7778_register_hpb_dmae(); } void __init r8a7778_init_late(void) { shmobile_init_late(); platform_device_register_full(&ehci_info); platform_device_register_full(&ohci_info); } static struct renesas_intc_irqpin_config irqpin_platform_data __initdata = { .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ .sense_bitfield_width = 2, }; static struct resource irqpin_resources[] __initdata = { DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */ DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */ DEFINE_RES_IRQ(gic_iid(0x3b)), /* IRQ0 */ DEFINE_RES_IRQ(gic_iid(0x3c)), /* IRQ1 */ DEFINE_RES_IRQ(gic_iid(0x3d)), /* IRQ2 */ DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */ }; void __init r8a7778_init_irq_extpin_dt(int irlm) { void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); unsigned long tmp; if (!icr0) { pr_warn("r8a7778: unable to setup external irq pin mode\n"); return; } tmp = ioread32(icr0); if (irlm) tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */ else tmp &= ~(1 << 23); /* IRL mode - not supported */ tmp |= (1 << 21); /* LVLMODE = 1 */ iowrite32(tmp, icr0); iounmap(icr0); } void __init r8a7778_init_irq_extpin(int irlm) { r8a7778_init_irq_extpin_dt(irlm); if (irlm) platform_device_register_resndata( NULL, "renesas_intc_irqpin", -1, irqpin_resources, ARRAY_SIZE(irqpin_resources), &irqpin_platform_data, sizeof(irqpin_platform_data)); } #ifdef CONFIG_USE_OF #define INT2SMSKCR0 0x82288 /* 0xfe782288 */ #define INT2SMSKCR1 0x8228c /* 0xfe78228c */ #define INT2NTSR0 0x00018 /* 0xfe700018 */ #define INT2NTSR1 0x0002c /* 0xfe70002c */ void __init r8a7778_init_irq_dt(void) { void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000); #ifdef CONFIG_ARCH_SHMOBILE_LEGACY void __iomem *gic_dist_base = ioremap_nocache(0xfe438000, 0x1000); void __iomem *gic_cpu_base = ioremap_nocache(0xfe430000, 0x1000); #endif BUG_ON(!base); #ifdef CONFIG_ARCH_SHMOBILE_LEGACY gic_init(0, 29, gic_dist_base, gic_cpu_base); #else irqchip_init(); #endif /* route all interrupts to ARM */ __raw_writel(0x73ffffff, base + INT2NTSR0); __raw_writel(0xffffffff, base + INT2NTSR1); /* unmask all known interrupts in INTCS2 */ __raw_writel(0x08330773, base + INT2SMSKCR0); __raw_writel(0x00311110, base + INT2SMSKCR1); iounmap(base); }
/* * FIXME: Should we set up the GPIO domain here? * * The problem is that we cannot put the interrupt resources into the platform * device until the irqdomain has been added. Right now, we set the GIC interrupt * domain from init_irq(), then load the gpio driver from * core_initcall(nmk_gpio_init) and add the platform devices from * arch_initcall(customize_machine). * * This feels fragile because it depends on the gpio device getting probed * _before_ any device uses the gpio interrupts. */ void __init ux500_init_irq(void) { struct device_node *np; struct resource r; irqchip_init(); np = of_find_compatible_node(NULL, NULL, "stericsson,db8500-prcmu"); of_address_to_resource(np, 0, &r); of_node_put(np); if (!r.start) { pr_err("could not find PRCMU base resource\n"); return; } prcmu_early_init(r.start, r.end-r.start); ux500_pm_init(r.start, r.end-r.start); /* * Init clocks here so that they are available for system timer * initialization. */ if (cpu_is_u8500_family()) u8500_clk_init(); else if (cpu_is_u9540()) u9540_clk_init(); else if (cpu_is_u8540()) u8540_clk_init(); }
static void __init imx7d_init_irq(void) { imx_init_revision_from_anatop(); imx_src_init(); imx_gpcv2_init(); irqchip_init(); }
static void __init tegra_dt_init_irq(void) { tegra_pmc_init_irq(); tegra_init_irq(); irqchip_init(); tegra_legacy_irq_syscore_init(); }
void __init r8a7740_init_irq_of(void) { void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10); void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10); void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4); irqchip_init(); /* route signals to GIC */ iowrite32(0x0, pfc_inta_ctrl); /* * To mask the shared interrupt to SPI 149 we must ensure to set * PRIO *and* MASK. Else we run into IRQ floods when registering * the intc_irqpin devices */ iowrite32(0x0, intc_prio_base + 0x0); iowrite32(0x0, intc_prio_base + 0x4); iowrite32(0x0, intc_prio_base + 0x8); iowrite32(0x0, intc_prio_base + 0xc); iowrite8(0xff, intc_msk_base + 0x0); iowrite8(0xff, intc_msk_base + 0x4); iowrite8(0xff, intc_msk_base + 0x8); iowrite8(0xff, intc_msk_base + 0xc); iounmap(intc_prio_base); iounmap(intc_msk_base); iounmap(pfc_inta_ctrl); }
void __init init_IRQ(void) { init_irq_stacks(); irqchip_init(); if (!handle_arch_irq) panic("No interrupt controller found."); }
static void __init imx6q_init_irq(void) { imx_init_revision_from_anatop(); imx_init_l2cache(); imx_src_init(); imx_gpc_init(); irqchip_init(); }
void __init arch_init_irq(void) { irqchip_init(); pr_info("GIC: %spresent\n", (gic_present) ? "" : "not "); pr_info("EIC: %s\n", (current_cpu_data.options & MIPS_CPU_VEIC) ? "on" : "off"); }
static void __init socfpga_arria10_init_irq(void) { irqchip_init(); socfpga_sysmgr_init(); if (IS_ENABLED(CONFIG_EDAC_ALTERA_L2C)) socfpga_init_arria10_l2_ecc(); if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM)) socfpga_init_arria10_ocram_ecc(); }
static void __init imx6sx_init_irq(void) { imx_gpc_check_dt(); imx_init_revision_from_anatop(); imx_init_l2cache(); imx_src_init(); irqchip_init(); imx6_pm_ccm_init("fsl,imx6sx-ccm"); }
void __init arch_init_irq(void) { int corehi_irq; /* * Preallocate the i8259's expected virq's here. Since irqchip_init() * will probe the irqchips in hierarchial order, i8259 is probed last. * If anything allocates a virq before the i8259 is probed, it will * be given one of the i8259's expected range and consequently setup * of the i8259 will fail. */ WARN(irq_alloc_descs(I8259A_IRQ_BASE, I8259A_IRQ_BASE, 16, numa_node_id()) < 0, "Cannot reserve i8259 virqs at IRQ%d\n", I8259A_IRQ_BASE); i8259_set_poll(mips_pcibios_iack); irqchip_init(); switch (mips_revision_sconid) { case MIPS_REVISION_SCON_SOCIT: case MIPS_REVISION_SCON_ROCIT: if (cpu_has_veic) init_msc_irqs(MIPS_MSC01_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); else init_msc_irqs(MIPS_MSC01_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); break; case MIPS_REVISION_SCON_SOCITSC: case MIPS_REVISION_SCON_SOCITSCP: if (cpu_has_veic) init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); else init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); } if (gic_present) { corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI; } else if (cpu_has_veic) { set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch); corehi_irq = MSC01E_INT_BASE + MSC01E_INT_COREHI; } else { corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI; } setup_irq(corehi_irq, &corehi_irqaction); }
void __init arch_init_irq(void) { struct device_node *dn; /* Only these controllers support SMP IRQ affinity */ dn = of_find_matching_node(NULL, smp_intc_dt_match); if (dn) of_node_put(dn); else bmips_tp1_irqs = 0; irqchip_init(); }
static void __init r8a7779_init_irq_dt(void) { irqchip_init(); /* route all interrupts to ARM */ __raw_writel(0xffffffff, INT2NTSR0); __raw_writel(0x3fffffff, INT2NTSR1); /* unmask all known interrupts in INTCS2 */ __raw_writel(0xfffffff0, INT2SMSKCR0); __raw_writel(0xfff7ffff, INT2SMSKCR1); __raw_writel(0xfffbffdf, INT2SMSKCR2); __raw_writel(0xbffffffc, INT2SMSKCR3); __raw_writel(0x003fee3f, INT2SMSKCR4); }
/* * Late Interrupt system init called from start_kernel for Boot CPU only * * Since slab must already be initialized, platforms can start doing any * needed request_irq( )s */ void __init init_IRQ(void) { /* Any external intc can be setup here */ if (machine_desc->init_irq) machine_desc->init_irq(); /* process the entire interrupt tree in one go */ irqchip_init(); #ifdef CONFIG_SMP /* Master CPU can initialize it's side of IPI */ if (machine_desc->init_smp) machine_desc->init_smp(smp_processor_id()); #endif }
/* IRQ for DMA channels */ DEFINE_RES_NAMED(gic_iid(0x7b), 5, NULL, IORESOURCE_IRQ), }; static void __init r8a7778_register_hpb_dmae(void) { platform_device_register_resndata(&platform_bus, "hpb-dma-engine", -1, hpb_dmae_resources, ARRAY_SIZE(hpb_dmae_resources), &dma_platform_data, sizeof(dma_platform_data)); } void __init r8a7778_add_standard_devices(void) { r8a7778_add_dt_devices(); r8a7778_register_scif(0); r8a7778_register_scif(1); r8a7778_register_scif(2); r8a7778_register_scif(3); r8a7778_register_scif(4); r8a7778_register_scif(5); r8a7778_register_i2c(0); r8a7778_register_i2c(1); r8a7778_register_i2c(2); r8a7778_register_i2c(3); r8a7778_register_hspi(0); r8a7778_register_hspi(1); r8a7778_register_hspi(2); r8a7778_register_hpb_dmae(); } void __init r8a7778_init_late(void) { platform_device_register_full(&ehci_info); platform_device_register_full(&ohci_info); } static struct renesas_intc_irqpin_config irqpin_platform_data __initdata = { .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ .sense_bitfield_width = 2, }; static struct resource irqpin_resources[] __initdata = { DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */ DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */ DEFINE_RES_IRQ(gic_iid(0x3b)), /* IRQ0 */ DEFINE_RES_IRQ(gic_iid(0x3c)), /* IRQ1 */ DEFINE_RES_IRQ(gic_iid(0x3d)), /* IRQ2 */ DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */ }; void __init r8a7778_init_irq_extpin_dt(int irlm) { void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); unsigned long tmp; if (!icr0) { pr_warn("r8a7778: unable to setup external irq pin mode\n"); return; } tmp = ioread32(icr0); if (irlm) tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */ else tmp &= ~(1 << 23); /* IRL mode - not supported */ tmp |= (1 << 21); /* LVLMODE = 1 */ iowrite32(tmp, icr0); iounmap(icr0); } void __init r8a7778_init_irq_extpin(int irlm) { r8a7778_init_irq_extpin_dt(irlm); if (irlm) platform_device_register_resndata( &platform_bus, "renesas_intc_irqpin", -1, irqpin_resources, ARRAY_SIZE(irqpin_resources), &irqpin_platform_data, sizeof(irqpin_platform_data)); } void __init r8a7778_init_delay(void) { shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */ } #ifdef CONFIG_USE_OF #define INT2SMSKCR0 0x82288 /* 0xfe782288 */ #define INT2SMSKCR1 0x8228c /* 0xfe78228c */ #define INT2NTSR0 0x00018 /* 0xfe700018 */ #define INT2NTSR1 0x0002c /* 0xfe70002c */ void __init r8a7778_init_irq_dt(void) { void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000); BUG_ON(!base); irqchip_init(); /* route all interrupts to ARM */ __raw_writel(0x73ffffff, base + INT2NTSR0); __raw_writel(0xffffffff, base + INT2NTSR1); /* unmask all known interrupts in INTCS2 */ __raw_writel(0x08330773, base + INT2SMSKCR0); __raw_writel(0x00311110, base + INT2SMSKCR1); iounmap(base); }
void __init init_IRQ(void) { int ret; if (IS_ENABLED(CONFIG_OF) && !machine_desc->init_irq) irqchip_init(); else machine_desc->init_irq(); if (IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_CACHE_L2X0) && (machine_desc->l2c_aux_mask || machine_desc->l2c_aux_val)) { if (!outer_cache.write_sec) outer_cache.write_sec = machine_desc->l2c_write_sec; ret = l2x0_of_init(machine_desc->l2c_aux_val, machine_desc->l2c_aux_mask); if (ret) pr_err("L2C: failed to init: %d\n", ret); } }
/* * FIXME: Should we set up the GPIO domain here? * * The problem is that we cannot put the interrupt resources into the platform * device until the irqdomain has been added. Right now, we set the GIC interrupt * domain from init_irq(), then load the gpio driver from * core_initcall(nmk_gpio_init) and add the platform devices from * arch_initcall(customize_machine). * * This feels fragile because it depends on the gpio device getting probed * _before_ any device uses the gpio interrupts. */ void __init ux500_init_irq(void) { void __iomem *dist_base; void __iomem *cpu_base; gic_arch_extn.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND; if (cpu_is_u8500_family() || cpu_is_ux540_family()) { dist_base = __io_address(U8500_GIC_DIST_BASE); cpu_base = __io_address(U8500_GIC_CPU_BASE); } else ux500_unknown_soc(); #ifdef CONFIG_OF if (of_have_populated_dt()) irqchip_init(); else #endif gic_init(0, 29, dist_base, cpu_base); /* * Init clocks here so that they are available for system timer * initialization. */ if (cpu_is_u8500_family()) { prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1); ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1); u8500_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE, U8500_CLKRST3_BASE, U8500_CLKRST5_BASE, U8500_CLKRST6_BASE); } else if (cpu_is_u9540()) { prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1); ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1); u8500_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE, U8500_CLKRST3_BASE, U8500_CLKRST5_BASE, U8500_CLKRST6_BASE); } else if (cpu_is_u8540()) { prcmu_early_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1); ux500_pm_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1); u8540_clk_init(); } }
void __init arch_init_irq(void) { if (mips_machtype == ATH79_MACH_GENERIC_OF) { irqchip_init(); return; } if (soc_is_ar71xx() || soc_is_ar724x() || soc_is_ar913x() || soc_is_ar933x()) { irq_wb_chan[2] = 3; irq_wb_chan[3] = 2; } else if (soc_is_ar934x()) { irq_wb_chan[3] = 2; } mips_cpu_irq_init(); ath79_misc_irq_init(); if (soc_is_ar934x()) ar934x_ip2_irq_init(); else if (soc_is_qca955x()) qca955x_irq_init(); }
void __init r8a7779_init_irq_dt(void) { #ifdef CONFIG_ARCH_SHMOBILE_LEGACY void __iomem *gic_dist_base = ioremap_nocache(0xf0001000, 0x1000); void __iomem *gic_cpu_base = ioremap_nocache(0xf0000100, 0x1000); #endif gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE); #ifdef CONFIG_ARCH_SHMOBILE_LEGACY gic_init(0, 29, gic_dist_base, gic_cpu_base); #else irqchip_init(); #endif /* route all interrupts to ARM */ __raw_writel(0xffffffff, INT2NTSR0); __raw_writel(0x3fffffff, INT2NTSR1); /* unmask all known interrupts in INTCS2 */ __raw_writel(0xfffffff0, INT2SMSKCR0); __raw_writel(0xfff7ffff, INT2SMSKCR1); __raw_writel(0xfffbffdf, INT2SMSKCR2); __raw_writel(0xbffffffc, INT2SMSKCR3); __raw_writel(0x003fee3f, INT2SMSKCR4); }
void __init arch_init_irq(void) { irqchip_init(); }
void __init init_IRQ(void) { irqchip_init(); }
void __init init_IRQ(void) { setup_vector(); irqchip_init(); }
void __init init_IRQ(void) { /* process the entire interrupt tree in one go */ irqchip_init(); }
static void __init intcp_init_irq_of(void) { cm_init(); irqchip_init(); }
void __init r8a7779_init_irq_dt(void) { irqchip_init(); r8a7779_init_irq_common(); }
static void __init sh_of_init_irq(void) { pr_info("SH generic board support: scanning for interrupt controllers\n"); irqchip_init(); }