/**
* Setup DPI timing for video mode MIPI panel.
* NOTE: do NOT modify this function
*/
static void __mdfld_dsi_dpi_set_timing(struct mdfld_dsi_config *config,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{
struct mdfld_dsi_dpi_timing dpi_timing;
struct mdfld_dsi_hw_context *ctx;
if (!config) {
DRM_ERROR("Invalid parameters\n");
return;
}
struct drm_device *dev = config->dev;
mode = adjusted_mode;
ctx = &config->dsi_hw_context;
mutex_lock(&config->context_lock);
/*dpi resolution*/
if (is_dual_dsi(dev))
ctx->dpi_resolution = (mode->vdisplay << 16 | (mode->hdisplay / 2));
else
ctx->dpi_resolution = (mode->vdisplay << 16 | mode->hdisplay);
/*Calculate DPI timing*/
mdfld_dsi_dpi_timing_calculation(dev, mode, &dpi_timing,
config->lane_count,
config->bpp);
/*update HW context with new DPI timings*/
ctx->hsync_count = dpi_timing.hsync_count;
ctx->hbp_count = dpi_timing.hbp_count;
ctx->hfp_count = dpi_timing.hfp_count;
ctx->hactive_count = dpi_timing.hactive_count;
ctx->vsync_count = dpi_timing.vsync_count;
ctx->vbp_count = dpi_timing.vbp_count;
ctx->vfp_count = dpi_timing.vfp_count;
mutex_unlock(&config->context_lock);
}
/**
* Power off sequence for DBI interface
*/
int __dbi_power_off(struct mdfld_dsi_config *dsi_config)
{
struct mdfld_dsi_hw_registers *regs;
struct mdfld_dsi_hw_context *ctx;
struct drm_device *dev;
struct drm_psb_private *dev_priv;
int pipe0_enabled;
int pipe2_enabled;
int err = 0;
u32 guit_val = 0;
u32 power_island = 0;
int retry;
int offset = 0;
if (!dsi_config)
return -EINVAL;
PSB_DEBUG_ENTRY("\n");
regs = &dsi_config->regs;
ctx = &dsi_config->dsi_hw_context;
dev = dsi_config->dev;
dev_priv = dev->dev_private;
/*Disable plane*/
REG_WRITE(regs->dspcntr_reg, 0);
/*Disable pipe*/
/* Don't disable DSR mode. */
REG_WRITE(regs->pipeconf_reg, (REG_READ(regs->pipeconf_reg) & ~BIT31));
/*wait for pipe disabling,
pipe synchronization plus , only avaiable when
timer generator is working*/
if (REG_READ(regs->mipi_reg) & BIT31) {
retry = 100000;
while (--retry && (REG_READ(regs->pipeconf_reg) & BIT30))
udelay(5);
if (!retry) {
DRM_ERROR("Failed to disable pipe\n");
err = -EAGAIN;
goto power_off_err;
}
}
if (!is_dual_dsi(dev)) {
/*enter ULPS*/
__dbi_enter_ulps_locked(dsi_config, offset);
} else {
/*Disable MIPI port*/
REG_WRITE(regs->mipi_reg, (REG_READ(regs->mipi_reg) & ~BIT31));
/*clear Low power output hold*/
REG_WRITE(regs->mipi_reg, (REG_READ(regs->mipi_reg) & ~BIT16));
/*Disable DSI controller*/
REG_WRITE(regs->device_ready_reg, (ctx->device_ready & ~BIT0));
/*enter ULPS*/
__dbi_enter_ulps_locked(dsi_config, offset);
offset = 0x1000;
/*Disable MIPI port*/
REG_WRITE(regs->mipi_reg +offset,
(REG_READ(regs->mipi_reg + offset) & ~BIT31));
/*clear Low power output hold*/
REG_WRITE(regs->mipi_reg + offset,
(REG_READ(regs->mipi_reg + offset) & ~BIT16));
offset = 0x800;
/*Disable DSI controller*/
REG_WRITE(regs->device_ready_reg + offset, (ctx->device_ready & ~BIT0));
/*enter ULPS*/
__dbi_enter_ulps_locked(dsi_config, offset);
offset = 0x0;
}
power_off_err:
power_island = pipe_to_island(dsi_config->pipe);
if (power_island & (OSPM_DISPLAY_A | OSPM_DISPLAY_C))
power_island |= OSPM_DISPLAY_MIO;
if (is_dual_dsi(dev))
power_island |= OSPM_DISPLAY_C;
if (!power_island_put(power_island))
return -EINVAL;
return err;
}
/**
* Power on sequence for command mode MIPI panel.
* NOTE: do NOT modify this function
*/
static int __dbi_panel_power_on(struct mdfld_dsi_config *dsi_config,
struct panel_funcs *p_funcs)
{
struct mdfld_dsi_hw_registers *regs;
struct mdfld_dsi_hw_context *ctx;
struct drm_psb_private *dev_priv;
struct drm_device *dev;
int reset_count = 10;
int err = 0;
struct mdfld_dsi_pkg_sender *sender
= mdfld_dsi_get_pkg_sender(dsi_config);
struct mdfld_dbi_dsr_info *dsr_info;
struct mdfld_dsi_dbi_output **dbi_outputs;
struct mdfld_dsi_dbi_output *dbi_output;
if (!sender) {
DRM_ERROR("pkg sender is NULL\n");
return -EINVAL;
}
PSB_DEBUG_ENTRY("\n");
if (!dsi_config)
return -EINVAL;
regs = &dsi_config->regs;
ctx = &dsi_config->dsi_hw_context;
dev = dsi_config->dev;
dev_priv = dev->dev_private;
mdfld_dsi_dsr_forbid_locked(dsi_config);
reset_recovery:
--reset_count;
err = 0;
/*after entering dstb mode, need reset*/
if (p_funcs && p_funcs->exit_deep_standby)
p_funcs->exit_deep_standby(dsi_config);
if (__dbi_power_on(dsi_config)) {
DRM_ERROR("Failed to init display controller!\n");
err = -EAGAIN;
goto power_on_err;
}
/**
* Different panel may have different ways to have
* drvIC initialized. Support it!
*/
if (p_funcs && p_funcs->drv_ic_init) {
if (p_funcs->drv_ic_init(dsi_config)) {
DRM_ERROR("Failed to init dsi controller!\n");
err = -EAGAIN;
goto power_on_err;
}
}
/* Issue "write_mem_start" DSI command during power on. */
dsr_info = dev_priv->dbi_dsr_info;
dbi_outputs = dsr_info->dbi_outputs;
dbi_output = dsi_config->pipe ? dbi_outputs[1] : dbi_outputs[0];
if (!IS_ANN_A0(dev))
intel_dsi_dbi_update_fb(dbi_output);
/**
* Different panel may have different ways to have
* panel turned on. Support it!
*/
if (p_funcs && p_funcs->power_on)
if (p_funcs->power_on(dsi_config)) {
DRM_ERROR("Failed to power on panel\n");
err = -EAGAIN;
goto power_on_err;
}
if (p_funcs && p_funcs->set_brightness)
if (p_funcs->set_brightness(dsi_config,
ctx->lastbrightnesslevel))
DRM_ERROR("Failed to set panel brightness\n");
/*wait for all FIFOs empty*/
mdfld_dsi_wait_for_fifos_empty(sender);
if (is_dual_dsi(dev)) {
sender->work_for_slave_panel = true;
mdfld_dsi_wait_for_fifos_empty(sender);
sender->work_for_slave_panel = false;
}
if (IS_ANN_A0(dev))
intel_dsi_dbi_update_fb(dbi_output);
power_on_err:
if (err && reset_count) {
DRM_ERROR("Failed to init panel, try reset it again!\n");
goto reset_recovery;
}
mdfld_dsi_dsr_allow_locked(dsi_config);
return err;
}
/* dbi interface power on*/
int __dbi_power_on(struct mdfld_dsi_config *dsi_config)
{
u32 val = 0;
struct mdfld_dsi_hw_registers *regs;
struct mdfld_dsi_hw_context *ctx;
struct drm_psb_private *dev_priv;
struct drm_device *dev;
int retry;
int err = 0;
u32 guit_val = 0;
u32 power_island = 0;
u32 sprite_reg_offset = 0;
int i = 0;
int offset = 0;
PSB_DEBUG_ENTRY("\n");
if (!dsi_config)
return -EINVAL;
regs = &dsi_config->regs;
ctx = &dsi_config->dsi_hw_context;
dev = dsi_config->dev;
dev_priv = dev->dev_private;
power_island = pipe_to_island(dsi_config->pipe);
if (power_island & (OSPM_DISPLAY_A | OSPM_DISPLAY_C))
power_island |= OSPM_DISPLAY_MIO;
if (is_dual_dsi(dev))
power_island |= OSPM_DISPLAY_C;
if (!power_island_get(power_island))
return -EAGAIN;
/*
* Wait for DSI PLL locked on pipe, and only need to poll status of pipe
* A as both MIPI pipes share the same DSI PLL.
*/
if (dsi_config->pipe == 0) {
retry = 20000;
while (!(REG_READ(regs->pipeconf_reg) & PIPECONF_DSIPLL_LOCK) &&
--retry)
udelay(150);
if (!retry) {
DRM_ERROR("PLL failed to lock on pipe\n");
err = -EAGAIN;
goto power_on_err;
}
}
if (IS_ANN_A0(dev)) {
/* FIXME: reset the DC registers for ANN A0 */
power_island_get(OSPM_DISPLAY_B | OSPM_DISPLAY_C);
REG_WRITE(DSPCLK_GATE_D, 0xFFFFFFFF); /* 0x10000000 */
REG_WRITE(RAMCLK_GATE_D, 0xFFFFFFFF); /* 0x0 */
REG_WRITE(PFIT_CONTROL, 0x20000000);
REG_WRITE(DSPIEDCFGSHDW, 0x0);
REG_WRITE(DSPARB2, 0x000A0200);
REG_WRITE(DSPARB, 0x18040080);
REG_WRITE(DSPFW1, 0x0F0F3F3F);
REG_WRITE(DSPFW2, 0x5F2F0F3F);
REG_WRITE(DSPFW3, 0x0);
REG_WRITE(DSPFW4, 0x07071F1F);
REG_WRITE(DSPFW5, 0x2F17071F);
REG_WRITE(DSPFW6, 0x00001F3F);
REG_WRITE(DSPFW7, 0x1F3F1F3F);
REG_WRITE(DSPSRCTRL, 0x00080100);
REG_WRITE(DSPCHICKENBIT, 0x0);
REG_WRITE(FBDC_CHICKEN, 0x0C0C0C0C);
REG_WRITE(CURACNTR, 0x0);
REG_WRITE(CURBCNTR, 0x0);
REG_WRITE(CURCCNTR, 0x0);
REG_WRITE(IEP_OVA_CTRL, 0x0);
REG_WRITE(IEP_OVA_CTRL, 0x0);
REG_WRITE(DSPACNTR, 0x0);
REG_WRITE(DSPBCNTR, 0x0);
REG_WRITE(DSPCCNTR, 0x0);
REG_WRITE(DSPDCNTR, 0x0);
REG_WRITE(DSPECNTR, 0x0);
REG_WRITE(DSPFCNTR, 0x0);
power_island_put(OSPM_DISPLAY_B | OSPM_DISPLAY_C);
}
/*exit ULPS*/
if (__dbi_exit_ulps_locked(dsi_config, 0)) {
DRM_ERROR("Failed to exit ULPS\n");
goto power_on_err;
}
/*update MIPI port config*/
REG_WRITE(regs->mipi_reg, ctx->mipi |
REG_READ(regs->mipi_reg));
/*unready dsi adapter for re-programming*/
REG_WRITE(regs->device_ready_reg,
REG_READ(regs->device_ready_reg) & ~(DSI_DEVICE_READY));
if (is_dual_dsi(dev)) {
if (__dbi_exit_ulps_locked(dsi_config, 0x800)) {
DRM_ERROR("Failed to exit ULPS\n");
goto power_on_err;
}
offset = 0x1000;
REG_WRITE(regs->mipi_reg + offset, ctx->mipi |
REG_READ(regs->mipi_reg + offset));
/*unready dsi adapter for re-programming*/
offset = 0x800;
REG_WRITE(regs->device_ready_reg + offset,
REG_READ(regs->device_ready_reg + offset) & ~(DSI_DEVICE_READY));
}
/*
* According to MIPI D-PHY spec, if clock stop feature is enabled (EOT
* Disable), un-ready MIPI adapter needs to wait for 20 cycles from HS
* to LP mode. Per calculation 1us is enough.
*/
if (ctx->eot_disable & CLOCK_STOP)
udelay(1);
__dbi_set_properties(dsi_config, PORT_A);
/*Setup pipe timing*/
REG_WRITE(regs->htotal_reg, ctx->htotal);
REG_WRITE(regs->hblank_reg, ctx->hblank);
REG_WRITE(regs->hsync_reg, ctx->hsync);
REG_WRITE(regs->vtotal_reg, ctx->vtotal);
REG_WRITE(regs->vblank_reg, ctx->vblank);
REG_WRITE(regs->vsync_reg, ctx->vsync);
REG_WRITE(regs->pipesrc_reg, ctx->pipesrc);
REG_WRITE(regs->dsppos_reg, ctx->dsppos);
REG_WRITE(regs->dspstride_reg, ctx->dspstride);
if (!IS_ANN_A0(dev)) {
/*restore color_coef (chrome) */
for (i = 0; i < 6; i++)
REG_WRITE(regs->color_coef_reg + (i<<2), ctx->color_coef[i]);
/* restore palette (gamma) */
for (i = 0; i < 256; i++)
REG_WRITE(regs->palette_reg + (i<<2), ctx->palette[i]);
/* restore dpst setting */
if (dev_priv->psb_dpst_state) {
dpstmgr_reg_restore_locked(dev, dsi_config);
psb_enable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
}
}
/*Setup plane*/
REG_WRITE(regs->dspsize_reg, ctx->dspsize);
REG_WRITE(regs->dspsurf_reg, ctx->dspsurf);
REG_WRITE(regs->dsplinoff_reg, ctx->dsplinoff);
REG_WRITE(regs->vgacntr_reg, ctx->vgacntr);
if (is_dual_dsi(dev))
__dbi_set_properties(dsi_config, PORT_C);
/*enable plane*/
val = ctx->dspcntr | BIT31;
REG_WRITE(regs->dspcntr_reg, val);
if (ctx->sprite_dspcntr & BIT31) {
if (dsi_config->pipe == 0)
sprite_reg_offset = 0x3000;
else if (dsi_config->pipe == 2)
sprite_reg_offset = 0x1000;
/* Set up Sprite Plane */
REG_WRITE(regs->dspsize_reg + sprite_reg_offset,
ctx->sprite_dspsize);
REG_WRITE(regs->dspsurf_reg + sprite_reg_offset,
ctx->sprite_dspsurf);
REG_WRITE(regs->dsplinoff_reg + sprite_reg_offset,
ctx->sprite_dsplinoff);
REG_WRITE(regs->dsppos_reg + sprite_reg_offset,
ctx->sprite_dsppos);
REG_WRITE(regs->dspstride_reg + sprite_reg_offset,
ctx->sprite_dspstride);
/* enable plane */
REG_WRITE(regs->dspcntr_reg + sprite_reg_offset,
ctx->sprite_dspcntr);
}
/* Set up Overlay Plane */
if (ctx->ovaadd)
PSB_WVDC32(ctx->ovaadd, OV_OVADD);
if (ctx->ovcadd)
PSB_WVDC32(ctx->ovcadd, OVC_OVADD);
/*ready dsi adapter*/
REG_WRITE(regs->device_ready_reg,
REG_READ(regs->device_ready_reg) | DSI_DEVICE_READY);
mdelay(1);
if (is_dual_dsi(dev)) {
REG_WRITE(regs->device_ready_reg + offset,
REG_READ(regs->device_ready_reg + offset) | DSI_DEVICE_READY);
}
if (IS_ANN_A0(dev)) {
REG_WRITE(regs->ddl1_reg, ctx->ddl1);
REG_WRITE(regs->ddl2_reg, ctx->ddl2);
REG_WRITE(regs->ddl3_reg, ctx->ddl3);
REG_WRITE(regs->ddl4_reg, ctx->ddl4);
}
/*Enable pipe*/
val = ctx->pipeconf;
val &= ~0x000c0000;
val |= BIT31 | PIPEACONF_DSR;
REG_WRITE(regs->pipeconf_reg, val);
/*Wait for pipe enabling,when timing generator is working */
retry = 10000;
while (--retry && !(REG_READ(regs->pipeconf_reg) & BIT30))
udelay(3);
if (!retry) {
DRM_ERROR("Failed to enable pipe\n");
err = -EAGAIN;
goto power_on_err;
}
/*
* Enable TE to trigger "write_mem_start" issuing
* in non-normal boot modes.
*/
mdfld_enable_te(dev, dsi_config->pipe);
return err;
power_on_err:
power_island_put(power_island);
return err;
}
/*
* Calculate the dpi time basing on a given drm mode @mode
* return 0 on success.
* FIXME: I was using proposed mode value for calculation, may need to
* use crtc mode values later
*/
int mdfld_dsi_dpi_timing_calculation(struct drm_device *dev,
struct drm_display_mode *mode,
struct mdfld_dsi_dpi_timing *dpi_timing,
int num_lane, int bpp)
{
int pclk_hsync, pclk_hfp, pclk_hbp, pclk_hactive;
int pclk_vsync, pclk_vfp, pclk_vbp, pclk_vactive;
if (!mode || !dpi_timing) {
DRM_ERROR("Invalid parameter\n");
return -EINVAL;
}
PSB_DEBUG_ENTRY("pclk %d, hdisplay %d, hsync_start %d, hsync_end %d," \
"htotal %d\n",
mode->clock, mode->hdisplay, mode->hsync_start,
mode->hsync_end, mode->htotal);
PSB_DEBUG_ENTRY("vdisplay %d, vsync_start %d, vsync_end %d," \
"vtotal %d\n",
mode->vdisplay, mode->vsync_start,
mode->vsync_end, mode->vtotal);
pclk_hactive = mode->hdisplay;
pclk_hfp = mode->hsync_start - mode->hdisplay;
pclk_hsync = mode->hsync_end - mode->hsync_start;
pclk_hbp = mode->htotal - mode->hsync_end;
pclk_vactive = mode->vdisplay;
pclk_vfp = mode->vsync_start - mode->vdisplay;
pclk_vsync = mode->vsync_end - mode->vsync_start;
pclk_vbp = mode->vtotal - mode->vsync_end;
/*
* byte clock counts were calculated by following formula
* bclock_count = pclk_count * bpp / num_lane / 8
*/
if (is_dual_dsi(dev)) {
dpi_timing->hsync_count = pclk_hsync;
dpi_timing->hbp_count = pclk_hbp;
dpi_timing->hfp_count = pclk_hfp;
dpi_timing->hactive_count = pclk_hactive;
dpi_timing->vsync_count = pclk_vsync;
dpi_timing->vbp_count = pclk_vbp;
dpi_timing->vfp_count = pclk_vfp;
} else {
dpi_timing->hsync_count =
mdfld_dsi_dpi_to_byte_clock_count(pclk_hsync, num_lane, bpp);
dpi_timing->hbp_count =
mdfld_dsi_dpi_to_byte_clock_count(pclk_hbp, num_lane, bpp);
dpi_timing->hfp_count =
mdfld_dsi_dpi_to_byte_clock_count(pclk_hfp, num_lane, bpp);
dpi_timing->hactive_count =
mdfld_dsi_dpi_to_byte_clock_count(pclk_hactive, num_lane, bpp);
dpi_timing->vsync_count =
mdfld_dsi_dpi_to_byte_clock_count(pclk_vsync, num_lane, bpp);
dpi_timing->vbp_count =
mdfld_dsi_dpi_to_byte_clock_count(pclk_vbp, num_lane, bpp);
dpi_timing->vfp_count =
mdfld_dsi_dpi_to_byte_clock_count(pclk_vfp, num_lane, bpp);
}
PSB_DEBUG_ENTRY("DPI timings: %d, %d, %d, %d, %d, %d, %d\n",
dpi_timing->hsync_count, dpi_timing->hbp_count,
dpi_timing->hfp_count, dpi_timing->hactive_count,
dpi_timing->vsync_count, dpi_timing->vbp_count,
dpi_timing->vfp_count);
return 0;
}
/**
* Power off sequence for video mode MIPI panel.
* NOTE: do NOT modify this function
*/
static int __dpi_panel_power_off(struct mdfld_dsi_config *dsi_config,
struct panel_funcs *p_funcs)
{
u32 val = 0;
u32 tmp = 0;
struct mdfld_dsi_hw_registers *regs;
struct mdfld_dsi_hw_context *ctx;
struct drm_device *dev;
struct drm_psb_private *dev_priv;
int retry;
int i;
int err = 0;
u32 guit_val = 0;
u32 power_island = 0;
int offset = 0;
PSB_DEBUG_ENTRY("\n");
if (!dsi_config)
return -EINVAL;
regs = &dsi_config->regs;
ctx = &dsi_config->dsi_hw_context;
dev = dsi_config->dev;
dev_priv = dev->dev_private;
/* Don't reset brightness to 0.*/
ctx->lastbrightnesslevel = psb_brightness;
tmp = REG_READ(regs->pipeconf_reg);
/*save color_coef (chrome) */
for (i = 0; i < 6; i++)
ctx->color_coef[i] = REG_READ(regs->color_coef_reg + (i<<2));
/* save palette (gamma) */
for (i = 0; i < 256; i++)
ctx->palette[i] = REG_READ(regs->palette_reg + (i<<2));
/*
* Couldn't disable the pipe until DRM_WAIT_ON signaled by last
* vblank event when playing video, otherwise the last vblank event
* will lost when pipe disabled before vblank interrupt coming
* sometimes.
*/
/*Disable panel*/
val = ctx->dspcntr;
REG_WRITE(regs->dspcntr_reg, (val & ~BIT31));
/*Disable overlay & cursor panel assigned to this pipe*/
REG_WRITE(regs->pipeconf_reg, (tmp | (0x000c0000)));
/*Disable pipe*/
val = REG_READ(regs->pipeconf_reg);
ctx->pipeconf = val;
REG_WRITE(regs->pipeconf_reg, (val & ~BIT31));
/*wait for pipe disabling,
pipe synchronization plus , only avaiable when
timer generator is working*/
if (REG_READ(regs->mipi_reg) & BIT31) {
retry = 100000;
while (--retry && (REG_READ(regs->pipeconf_reg) & BIT30))
udelay(5);
if (!retry) {
DRM_ERROR("Failed to disable pipe\n");
err = -EAGAIN;
goto power_off_err;
}
}
/**
* Different panel may have different ways to have
* panel turned off. Support it!
*/
if (p_funcs && p_funcs->power_off) {
if (p_funcs->power_off(dsi_config)) {
DRM_ERROR("Failed to power off panel\n");
err = -EAGAIN;
goto power_off_err;
}
}
/*Disable MIPI port*/
REG_WRITE(regs->mipi_reg, (REG_READ(regs->mipi_reg) & ~BIT31));
/*clear Low power output hold*/
REG_WRITE(regs->mipi_reg, (REG_READ(regs->mipi_reg) & ~BIT16));
/*Disable DSI controller*/
REG_WRITE(regs->device_ready_reg, (ctx->device_ready & ~BIT0));
/*enter ULPS*/
__dpi_enter_ulps_locked(dsi_config, offset);
if (is_dual_dsi(dev)) {
offset = 0x1000;
/*Disable MIPI port*/
REG_WRITE(regs->mipi_reg, (REG_READ(regs->mipi_reg) & ~BIT31));
/*clear Low power output hold*/
REG_WRITE(regs->mipi_reg, (REG_READ(regs->mipi_reg) & ~BIT16));
offset = 0x800;
/*Disable DSI controller*/
REG_WRITE(regs->device_ready_reg, (ctx->device_ready & ~BIT0));
/*enter ULPS*/
__dpi_enter_ulps_locked(dsi_config, offset);
offset = 0x0;
}
/* Disable DSI PLL */
intel_mid_msgbus_write32(CCK_PORT, DSI_PLL_DIV_REG, 0);
guit_val = intel_mid_msgbus_read32(CCK_PORT, DSI_PLL_CTRL_REG);
intel_mid_msgbus_write32(CCK_PORT, DSI_PLL_CTRL_REG, _DSI_LDO_EN);
power_off_err:
power_island = pipe_to_island(dsi_config->pipe);
if (power_island & (OSPM_DISPLAY_A | OSPM_DISPLAY_C))
power_island |= OSPM_DISPLAY_MIO;
if (is_dual_dsi(dev))
power_island |= OSPM_DISPLAY_C;
if (!power_island_put(power_island))
return -EINVAL;
return err;
}
/**
* Set up the display clock
*
*/
void mrfld_setup_pll(struct drm_device *dev, int pipe, int clk)
{
DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
int refclk = 0;
int clk_n = 0, clk_p2 = 0, clk_byte = 1, m_conv = 0, clk_tmp = 0;
struct mrst_clock_t clock;
bool ok;
u32 pll = 0, fp = 0;
bool is_mipi = false, is_mipi2 = false, is_hdmi = false;
struct mdfld_dsi_config *dsi_config = NULL;
struct mdfld_dsi_hw_context *ctx = NULL;
PSB_DEBUG_ENTRY("pipe = 0x%x\n", pipe);
if (pipe == 0)
dsi_config = dev_priv->dsi_configs[0];
else if (pipe == 2)
dsi_config = dev_priv->dsi_configs[1];
if ((pipe != 1) && !dsi_config) {
DRM_ERROR("Invalid DSI config\n");
return;
}
if (pipe != 1) {
ctx = &dsi_config->dsi_hw_context;
mutex_lock(&dsi_config->context_lock);
}
switch (pipe) {
case 0:
is_mipi = true;
break;
case 1:
is_hdmi = true;
break;
case 2:
is_mipi2 = true;
break;
}
if ((dev_priv->ksel == KSEL_CRYSTAL_19)
|| (dev_priv->ksel == KSEL_BYPASS_19)) {
refclk = 19200;
if (is_mipi || is_mipi2) {
clk_n = 1, clk_p2 = 8;
} else if (is_hdmi) {
clk_n = 1, clk_p2 = 10;
}
} else if (dev_priv->ksel == KSEL_BYPASS_25) {
refclk = 25000;
if (is_mipi || is_mipi2) {
clk_n = 1, clk_p2 = 8;
} else if (is_hdmi) {
clk_n = 1, clk_p2 = 10;
}
} else if ((dev_priv->ksel == KSEL_BYPASS_83_100)
&& (dev_priv->core_freq == 166)) {
refclk = 83000;
if (is_mipi || is_mipi2) {
clk_n = 4, clk_p2 = 8;
} else if (is_hdmi) {
clk_n = 4, clk_p2 = 10;
}
} else if ((dev_priv->ksel == KSEL_BYPASS_83_100) &&
(dev_priv->core_freq == 100 || dev_priv->core_freq == 200)) {
refclk = 100000;
if (is_mipi || is_mipi2) {
clk_n = 4, clk_p2 = 8;
} else if (is_hdmi) {
clk_n = 4, clk_p2 = 10;
}
}
if (is_mipi || is_mipi2)
clk_byte = 3;
clk_tmp = clk * clk_n * clk_p2 * clk_byte;
PSB_DEBUG_ENTRY("clk = %d, clk_n = %d, clk_p2 = %d. \n", clk, clk_n,
clk_p2);
PSB_DEBUG_ENTRY("clk = %d, clk_tmp = %d, clk_byte = %d. \n", clk,
clk_tmp, clk_byte);
ok = mrfld_find_best_PLL(dev, pipe, clk_tmp, refclk, &clock);
dev_priv->tmds_clock_khz = clock.dot / (clk_n * clk_p2 * clk_byte);
/*
* FIXME: Hard code the divisors' value for JDI panel, and need to
* calculate them according to the DSI PLL HAS spec.
*/
if (pipe != 1) {
switch(get_panel_type(dev, pipe)) {
case SDC_16x25_CMD:
clock.p1 = 3;
clock.m = 126;
break;
case SHARP_10x19_VID:
case SHARP_10x19_CMD:
clock.p1 = 3;
clock.m = 137;
break;
case SHARP_10x19_DUAL_CMD:
clock.p1 = 3;
clock.m = 125;
break;
case CMI_7x12_CMD:
clock.p1 = 4;
clock.m = 120;
break;
case SDC_25x16_CMD:
case JDI_25x16_CMD:
case SHARP_25x16_CMD:
clock.p1 = 3;
clock.m = 138;
break;
case SHARP_25x16_VID:
case JDI_25x16_VID:
clock.p1 = 3;
clock.m = 140;
break;
case JDI_7x12_VID:
clock.p1 = 5;
clk_n = 1;
clock.m = 144;
break;
case OTM1284A_VID:
if (Read_HW_ID() == HW_ID_EVB) {
clock.p1 = 3;
clock.m = 125;
}
break;
}
clk_n = 1;
}
if (!ok) {
DRM_ERROR("mdfldFindBestPLL fail in mrfld_crtc_mode_set.\n");
} else {
m_conv = mrfld_m_converts[(clock.m - MRFLD_M_MIN)];
PSB_DEBUG_ENTRY("dot clock = %d,"
"m = %d, p1 = %d, m_conv = %d. \n", clock.dot,
clock.m, clock.p1, m_conv);
}
/* Write the N1 & M1 parameters into DSI_PLL_DIV_REG */
fp = (clk_n / 2) << 16;
fp |= m_conv;
if (is_mipi) {
/* Enable DSI PLL clocks for DSI0 rather than CCK. */
pll |= _CLK_EN_PLL_DSI0;
pll &= ~_CLK_EN_CCK_DSI0;
/* Select DSI PLL as the source of the mux input clocks. */
pll &= ~_DSI_MUX_SEL_CCK_DSI0;
}
if (is_mipi2 || is_dual_dsi(dev)) {
/* Enable DSI PLL clocks for DSI1 rather than CCK. */
pll |= _CLK_EN_PLL_DSI1;
pll &= ~_CLK_EN_CCK_DSI1;
/* Select DSI PLL as the source of the mux input clocks. */
pll &= ~_DSI_MUX_SEL_CCK_DSI1;
}
if (is_hdmi)
pll |= MDFLD_VCO_SEL;
/* compute bitmask from p1 value */
pll |= (1 << (clock.p1 - 2)) << 17;
if (pipe != 1) {
ctx->dpll = pll;
ctx->fp = fp;
mutex_unlock(&dsi_config->context_lock);
}
}
/**
* Power on sequence for video mode MIPI panel.
* NOTE: do NOT modify this function
*/
static int __dpi_panel_power_on(struct mdfld_dsi_config *dsi_config,
struct panel_funcs *p_funcs)
{
u32 val = 0;
struct mdfld_dsi_hw_registers *regs;
struct mdfld_dsi_hw_context *ctx;
struct drm_psb_private *dev_priv;
struct drm_device *dev;
int retry, reset_count = 10;
int i;
int err = 0;
u32 guit_val = 0;
u32 power_island = 0;
int offset = 0;
PSB_DEBUG_ENTRY("\n");
if (!dsi_config)
return -EINVAL;
regs = &dsi_config->regs;
ctx = &dsi_config->dsi_hw_context;
dev = dsi_config->dev;
dev_priv = dev->dev_private;
power_island = pipe_to_island(dsi_config->pipe);
if (power_island & (OSPM_DISPLAY_A | OSPM_DISPLAY_C))
power_island |= OSPM_DISPLAY_MIO;
if (is_dual_dsi(dev))
power_island |= OSPM_DISPLAY_C;
if (!power_island_get(power_island))
return -EAGAIN;
reset_recovery:
--reset_count;
/*HW-Reset*/
if (p_funcs && p_funcs->reset)
p_funcs->reset(dsi_config);
if (!is_dual_dsi(dev)) {
/* Disable PLL*/
intel_mid_msgbus_write32(CCK_PORT, DSI_PLL_DIV_REG, 0);
guit_val = intel_mid_msgbus_read32(CCK_PORT, DSI_PLL_CTRL_REG);
intel_mid_msgbus_write32(CCK_PORT, DSI_PLL_CTRL_REG, _DSI_LDO_EN);
/* Program PLL */
intel_mid_msgbus_write32(CCK_PORT, DSI_PLL_DIV_REG, ctx->fp);
guit_val = intel_mid_msgbus_read32(CCK_PORT, DSI_PLL_CTRL_REG);
intel_mid_msgbus_write32(CCK_PORT, DSI_PLL_CTRL_REG,
((guit_val & ~_P1_POST_DIV_MASK) |
(ctx->dpll & _P1_POST_DIV_MASK)));
ctx->dpll |= DPLL_VCO_ENABLE;
ctx->dpll &= ~_DSI_LDO_EN;
intel_mid_msgbus_write32(CCK_PORT, DSI_PLL_CTRL_REG, ctx->dpll);
} else {
intel_mid_msgbus_write32(CCK_PORT, 0x68, 0x682);
/* Disable PLL*/
intel_mid_msgbus_write32(CCK_PORT, DSI_PLL_DIV_REG, 0);
guit_val = intel_mid_msgbus_read32(CCK_PORT, DSI_PLL_CTRL_REG);
intel_mid_msgbus_write32(CCK_PORT,
DSI_PLL_CTRL_REG,
_DSI_LDO_EN);
/* Program PLL */
intel_mid_msgbus_write32(CCK_PORT, DSI_PLL_DIV_REG, ctx->fp);
guit_val = intel_mid_msgbus_read32(CCK_PORT, DSI_PLL_CTRL_REG);
intel_mid_msgbus_write32(CCK_PORT, DSI_PLL_CTRL_REG,
((guit_val & ~_P1_POST_DIV_MASK) |
(ctx->dpll & _P1_POST_DIV_MASK)));
guit_val = intel_mid_msgbus_read32(CCK_PORT, DSI_PLL_CTRL_REG);
ctx->dpll |= DPLL_VCO_ENABLE;
ctx->dpll &= ~(_DSI_LDO_EN |
_CLK_EN_CCK_DSI0 | _CLK_EN_CCK_DSI1 |
_DSI_MUX_SEL_CCK_DSI1 | _DSI_MUX_SEL_CCK_DSI0);
ctx->dpll |= _CLK_EN_PLL_DSI0 | _CLK_EN_PLL_DSI1;
intel_mid_msgbus_write32(CCK_PORT, DSI_PLL_CTRL_REG, ctx->dpll);
}
/* Wait for DSI PLL lock */
retry = 10000;
guit_val = intel_mid_msgbus_read32(CCK_PORT, DSI_PLL_CTRL_REG);
while (((guit_val & _DSI_PLL_LOCK) != _DSI_PLL_LOCK) && (--retry)) {
udelay(3);
guit_val = intel_mid_msgbus_read32(CCK_PORT, DSI_PLL_CTRL_REG);
if (retry == 0) {
DRM_ERROR("DSI PLL fails to lock\n");
err = -EAGAIN;
goto power_on_err;
}
}
/*
* Wait for DSI PLL locked on pipe, and only need to poll status of pipe
* A as both MIPI pipes share the same DSI PLL.
*/
if (dsi_config->pipe == 0) {
retry = 20000;
while (!(REG_READ(regs->pipeconf_reg) & PIPECONF_DSIPLL_LOCK) &&
--retry)
udelay(150);
if (!retry) {
DRM_ERROR("PLL failed to lock on pipe\n");
err = -EAGAIN;
goto power_on_err;
}
}
__dpi_set_properties(dsi_config, PORT_A);
/*Setup pipe timing*/
REG_WRITE(regs->htotal_reg, ctx->htotal);
REG_WRITE(regs->hblank_reg, ctx->hblank);
REG_WRITE(regs->hsync_reg, ctx->hsync);
REG_WRITE(regs->vtotal_reg, ctx->vtotal);
REG_WRITE(regs->vblank_reg, ctx->vblank);
REG_WRITE(regs->vsync_reg, ctx->vsync);
REG_WRITE(regs->pipesrc_reg, ctx->pipesrc);
REG_WRITE(regs->dsppos_reg, ctx->dsppos);
REG_WRITE(regs->dspstride_reg, ctx->dspstride);
if (IS_ANN_A0(dev)) {
/*reset registers*/
REG_WRITE(0x7002C, 0x000A0200);
REG_WRITE(0x70508, 0x0c0c0c0c);
REG_WRITE(0x70504, 0xffffffff);
REG_WRITE(0x70500, 0xffffffff);
DRM_DEBUG("LOADING: 0x70504 %#x\n", REG_READ(0x70504));
}
/*Setup plane*/
REG_WRITE(regs->dspsize_reg, ctx->dspsize);
REG_WRITE(regs->dspsurf_reg, ctx->dspsurf);
REG_WRITE(regs->dsplinoff_reg, ctx->dsplinoff);
REG_WRITE(regs->vgacntr_reg, ctx->vgacntr);
/*restore color_coef (chrome) */
for (i = 0; i < 6; i++)
REG_WRITE(regs->color_coef_reg + (i<<2), ctx->color_coef[i]);
/* restore palette (gamma) */
for (i = 0; i < 256; i++)
REG_WRITE(regs->palette_reg + (i<<2), ctx->palette[i]);
/* restore dpst setting */
if (dev_priv->psb_dpst_state) {
dpstmgr_reg_restore_locked(dev, dsi_config);
psb_enable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
}
if (__dpi_config_port(dsi_config, p_funcs, PORT_A) != 0) {
if (!reset_count) {
err = -EAGAIN;
goto power_on_err;
}
DRM_ERROR("Failed to init dsi controller, reset it!\n");
goto reset_recovery;
}
if (is_dual_dsi(dev)) {
__dpi_set_properties(dsi_config, PORT_C);
__dpi_config_port(dsi_config, p_funcs, PORT_C);
}
/**
* Different panel may have different ways to have
* drvIC initialized. Support it!
*/
if (p_funcs && p_funcs->drv_ic_init) {
if (p_funcs->drv_ic_init(dsi_config)) {
if (!reset_count) {
err = -EAGAIN;
goto power_on_err;
}
DRM_ERROR("Failed to init dsi controller, reset it!\n");
goto reset_recovery;
}
}
/*Enable MIPI Port A*/
offset = 0x0;
REG_WRITE(regs->mipi_reg + offset, (ctx->mipi | BIT31));
REG_WRITE(regs->dpi_control_reg + offset, BIT1);
if (is_dual_dsi(dev)) {
/*Enable MIPI Port C*/
offset = 0x1000;
REG_WRITE(regs->mipi_reg + offset, (ctx->mipi | BIT31));
offset = 0x800;
REG_WRITE(regs->dpi_control_reg + offset, BIT1);
}
/**
* Different panel may have different ways to have
* panel turned on. Support it!
*/
if (p_funcs && p_funcs->power_on)
if (p_funcs->power_on(dsi_config)) {
DRM_ERROR("Failed to power on panel\n");
err = -EAGAIN;
goto power_on_err;
}
/*Enable pipe*/
val = ctx->pipeconf;
val &= ~0x000c0000;
val |= BIT31;
REG_WRITE(regs->pipeconf_reg, val);
/*Wait for pipe enabling,when timing generator
is wroking */
if (REG_READ(regs->mipi_reg) & BIT31) {
retry = 10000;
while (--retry && !(REG_READ(regs->pipeconf_reg) & BIT30))
udelay(3);
if (!retry) {
DRM_ERROR("Failed to enable pipe\n");
err = -EAGAIN;
goto power_on_err;
}
}
/*enable plane*/
val = ctx->dspcntr | BIT31;
REG_WRITE(regs->dspcntr_reg, val);
if (p_funcs && p_funcs->set_brightness) {
if (p_funcs->set_brightness(dsi_config,
ctx->lastbrightnesslevel))
DRM_ERROR("Failed to set panel brightness\n");
} else {
DRM_ERROR("Failed to set panel brightness\n");
}
if (p_funcs && p_funcs->drv_set_panel_mode)
p_funcs->drv_set_panel_mode(dsi_config);
psb_enable_vblank(dev, dsi_config->pipe);
return err;
power_on_err:
power_island_put(power_island);
return err;
}
/**
* Setup Display Controller to turn on/off a video mode panel.
* Most of the video mode MIPI panel should follow the power on/off
* sequence in this function.
* NOTE: do NOT modify this function for new panel Enabling. Register
* new panel function callbacks to make this function available for a
* new video mode panel
*/
static int __mdfld_dsi_dpi_set_power(struct drm_encoder *encoder, bool on)
{
struct mdfld_dsi_encoder *dsi_encoder;
struct mdfld_dsi_connector *dsi_connector;
struct mdfld_dsi_dpi_output *dpi_output;
struct mdfld_dsi_config *dsi_config;
struct panel_funcs *p_funcs;
int pipe;
struct drm_device *dev;
struct drm_psb_private *dev_priv;
if (!encoder) {
DRM_ERROR("Invalid encoder\n");
return -EINVAL;
}
dsi_encoder = MDFLD_DSI_ENCODER(encoder);
dpi_output = MDFLD_DSI_DPI_OUTPUT(dsi_encoder);
dsi_config = mdfld_dsi_encoder_get_config(dsi_encoder);
p_funcs = dpi_output->p_funcs;
pipe = mdfld_dsi_encoder_get_pipe(dsi_encoder);
dsi_connector = mdfld_dsi_encoder_get_connector(dsi_encoder);
if (!dsi_connector) {
DRM_ERROR("dsi_connector is NULL\n");
return -EINVAL;
}
dev = dsi_config->dev;
dev_priv = dev->dev_private;
if (dsi_connector->status != connector_status_connected)
return 0;
mutex_lock(&dsi_config->context_lock);
if (dpi_output->first_boot && on) {
if (dsi_config->dsi_hw_context.panel_on) {
if (IS_ANN(dev))
ann_dc_setup(dsi_config);
psb_enable_vblank(dev, dsi_config->pipe);
/* don't need ISLAND c for non dual-dsi panel */
if (!is_dual_dsi(dev))
power_island_put(OSPM_DISPLAY_C);
DRM_INFO("skip panle power setting for first boot! "
"panel is already powered on\n");
goto fun_exit;
}
if (android_hdmi_is_connected(dev))
otm_hdmi_power_islands_off();
/* power down islands turned on by firmware */
power_island_put(OSPM_DISPLAY_A | OSPM_DISPLAY_C |
OSPM_DISPLAY_MIO);
}
switch (on) {
case true:
/* panel is already on */
if (dsi_config->dsi_hw_context.panel_on)
goto fun_exit;
if (__dpi_panel_power_on(dsi_config, p_funcs, dpi_output->first_boot)) {
DRM_ERROR("Faild to turn on panel\n");
goto set_power_err;
}
dsi_config->dsi_hw_context.panel_on = 1;
/* for every dpi panel power on, clear the dpi underrun count */
dev_priv->pipea_dpi_underrun_count = 0;
dev_priv->pipec_dpi_underrun_count = 0;
break;
case false:
if (!dsi_config->dsi_hw_context.panel_on &&
!dpi_output->first_boot)
goto fun_exit;
if (__dpi_panel_power_off(dsi_config, p_funcs)) {
DRM_ERROR("Faild to turn off panel\n");
goto set_power_err;
}
dsi_config->dsi_hw_context.panel_on = 0;
break;
default:
break;
}
fun_exit:
mutex_unlock(&dsi_config->context_lock);
PSB_DEBUG_ENTRY("successfully\n");
return 0;
set_power_err:
mutex_unlock(&dsi_config->context_lock);
PSB_DEBUG_ENTRY("unsuccessfully!!!!\n");
return -EAGAIN;
}
/**
* Power on sequence for video mode MIPI panel.
* NOTE: do NOT modify this function
*/
static int __dpi_panel_power_on(struct mdfld_dsi_config *dsi_config,
struct panel_funcs *p_funcs, bool first_boot)
{
u32 val = 0;
struct mdfld_dsi_hw_registers *regs;
struct mdfld_dsi_hw_context *ctx;
struct drm_psb_private *dev_priv;
struct drm_device *dev;
int retry, reset_count = 10;
int i;
int err = 0;
u32 power_island = 0;
int offset = 0;
PSB_DEBUG_ENTRY("\n");
if (!dsi_config)
return -EINVAL;
regs = &dsi_config->regs;
ctx = &dsi_config->dsi_hw_context;
dev = dsi_config->dev;
dev_priv = dev->dev_private;
power_island = pipe_to_island(dsi_config->pipe);
if (power_island & (OSPM_DISPLAY_A | OSPM_DISPLAY_C))
power_island |= OSPM_DISPLAY_MIO;
if (is_dual_dsi(dev))
power_island |= OSPM_DISPLAY_C;
if (!power_island_get(power_island))
return -EAGAIN;
if (android_hdmi_is_connected(dev) && first_boot)
otm_hdmi_power_islands_on();
reset_recovery:
--reset_count;
/*HW-Reset*/
if (p_funcs && p_funcs->reset)
p_funcs->reset(dsi_config);
/*
* Wait for DSI PLL locked on pipe, and only need to poll status of pipe
* A as both MIPI pipes share the same DSI PLL.
*/
if (dsi_config->pipe == 0) {
retry = 20000;
while (!(REG_READ(regs->pipeconf_reg) & PIPECONF_DSIPLL_LOCK) &&
--retry)
udelay(150);
if (!retry) {
DRM_ERROR("PLL failed to lock on pipe\n");
err = -EAGAIN;
goto power_on_err;
}
}
if (IS_ANN(dev)) {
/* FIXME: reset the DC registers for ANN A0 */
ann_dc_setup(dsi_config);
}
__dpi_set_properties(dsi_config, PORT_A);
/* update 0x650c[0] = 1 to fixed arbitration pattern
* it is found display TLB request be blocked by display plane
* memory requests, never goes out. This causes display controller
* uses stale TLB data to do memory translation, getting wrong
* memory address for data, and causing the flickering issue.
*/
REG_WRITE(GCI_CTRL, REG_READ(GCI_CTRL) | 1);
/*Setup pipe timing*/
REG_WRITE(regs->htotal_reg, ctx->htotal);
REG_WRITE(regs->hblank_reg, ctx->hblank);
REG_WRITE(regs->hsync_reg, ctx->hsync);
REG_WRITE(regs->vtotal_reg, ctx->vtotal);
REG_WRITE(regs->vblank_reg, ctx->vblank);
REG_WRITE(regs->vsync_reg, ctx->vsync);
REG_WRITE(regs->pipesrc_reg, ctx->pipesrc);
REG_WRITE(regs->dsppos_reg, ctx->dsppos);
REG_WRITE(regs->dspstride_reg, ctx->dspstride);
/*Setup plane*/
REG_WRITE(regs->dspsize_reg, ctx->dspsize);
REG_WRITE(regs->dspsurf_reg, ctx->dspsurf);
REG_WRITE(regs->dsplinoff_reg, ctx->dsplinoff);
REG_WRITE(regs->vgacntr_reg, ctx->vgacntr);
/*restore color_coef (chrome) */
for (i = 0; i < 6; i++)
REG_WRITE(regs->color_coef_reg + (i<<2), csc_setting_save[i]);
/* restore palette (gamma) */
for (i = 0; i < 256; i++)
REG_WRITE(regs->palette_reg + (i<<2), gamma_setting_save[i]);
/* restore dpst setting */
if (dev_priv->psb_dpst_state) {
dpstmgr_reg_restore_locked(dev, dsi_config);
psb_enable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
}
if (__dpi_config_port(dsi_config, p_funcs, PORT_A) != 0) {
if (!reset_count) {
err = -EAGAIN;
goto power_on_err;
}
DRM_ERROR("Failed to init dsi controller, reset it!\n");
goto reset_recovery;
}
if (is_dual_dsi(dev)) {
__dpi_set_properties(dsi_config, PORT_C);
__dpi_config_port(dsi_config, p_funcs, PORT_C);
}
/**
* Different panel may have different ways to have
* drvIC initialized. Support it!
*/
if (p_funcs && p_funcs->drv_ic_init) {
if (p_funcs->drv_ic_init(dsi_config)) {
if (!reset_count) {
err = -EAGAIN;
goto power_on_err;
}
DRM_ERROR("Failed to init dsi controller, reset it!\n");
goto reset_recovery;
}
}
/*Enable MIPI Port A*/
offset = 0x0;
REG_WRITE(regs->mipi_reg + offset, (ctx->mipi | BIT31));
REG_WRITE(regs->dpi_control_reg + offset, BIT1);
if (is_dual_dsi(dev)) {
/*Enable MIPI Port C*/
offset = 0x1000;
REG_WRITE(regs->mipi_reg + offset, (ctx->mipi | BIT31));
offset = 0x800;
REG_WRITE(regs->dpi_control_reg + offset, BIT1);
}
/**
* Different panel may have different ways to have
* panel turned on. Support it!
*/
if (p_funcs && p_funcs->power_on)
if (p_funcs->power_on(dsi_config)) {
DRM_ERROR("Failed to power on panel\n");
err = -EAGAIN;
goto power_on_err;
}
if (IS_ANN(dev)) {
REG_WRITE(regs->ddl1_reg, ctx->ddl1);
REG_WRITE(regs->ddl2_reg, ctx->ddl2);
REG_WRITE(regs->ddl3_reg, ctx->ddl3);
REG_WRITE(regs->ddl4_reg, ctx->ddl4);
REG_WRITE(DSPARB2, ctx->dsparb2);
REG_WRITE(DSPARB, ctx->dsparb);
}
/*Enable pipe*/
val = ctx->pipeconf;
val &= ~0x000c0000;
/**
* Frame Start occurs on third HBLANK
* after the start of VBLANK
*/
val |= BIT31 | BIT28;
REG_WRITE(regs->pipeconf_reg, val);
/*Wait for pipe enabling,when timing generator
is wroking */
if (REG_READ(regs->mipi_reg) & BIT31) {
retry = 10000;
while (--retry && !(REG_READ(regs->pipeconf_reg) & BIT30))
udelay(3);
if (!retry) {
DRM_ERROR("Failed to enable pipe\n");
err = -EAGAIN;
goto power_on_err;
}
}
/*enable plane*/
val = ctx->dspcntr | BIT31;
REG_WRITE(regs->dspcntr_reg, val);
if (p_funcs && p_funcs->set_brightness) {
if (p_funcs->set_brightness(dsi_config,
ctx->lastbrightnesslevel))
DRM_ERROR("Failed to set panel brightness\n");
} else {
DRM_ERROR("Failed to set panel brightness\n");
}
if (p_funcs && p_funcs->drv_set_panel_mode)
p_funcs->drv_set_panel_mode(dsi_config);
psb_enable_vblank(dev, dsi_config->pipe);
return err;
power_on_err:
power_island_put(power_island);
return err;
}
/**
* Power off sequence for DBI interface
*/
int __dbi_power_off(struct mdfld_dsi_config *dsi_config)
{
struct mdfld_dsi_hw_registers *regs;
struct mdfld_dsi_hw_context *ctx;
struct drm_device *dev;
struct drm_psb_private *dev_priv;
int err = 0;
u32 power_island = 0;
int retry,i;
int offset = 0;
u32 val;
if (!dsi_config)
return -EINVAL;
PSB_DEBUG_ENTRY("\n");
regs = &dsi_config->regs;
ctx = &dsi_config->dsi_hw_context;
dev = dsi_config->dev;
dev_priv = dev->dev_private;
ctx->dspcntr = REG_READ(regs->dspcntr_reg);
ctx->pipeconf = REG_READ(regs->pipeconf_reg);
ctx->dsparb = REG_READ(DSPARB);
ctx->dsparb2 = REG_READ(DSPARB2);
/*save color_coef (chrome) */
for (i = 0; i < 6; i++)
ctx->color_coef[i] = REG_READ(regs->color_coef_reg + (i<<2));
/* save palette (gamma) */
for (i = 0; i < 256; i++)
ctx->palette[i] = REG_READ(regs->palette_reg + (i<<2));
/*Disable plane*/
val = ctx->dspcntr;
REG_WRITE(regs->dspcntr_reg, (val & ~BIT31));
/*Disable pipe*/
/* Don't disable DSR mode. */
REG_WRITE(regs->pipeconf_reg, (REG_READ(regs->pipeconf_reg) & ~BIT31));
/*wait for pipe disabling,
pipe synchronization plus , only avaiable when
timer generator is working*/
if (REG_READ(regs->mipi_reg) & BIT31) {
retry = 100000;
while (--retry && (REG_READ(regs->pipeconf_reg) & BIT30))
udelay(5);
if (!retry) {
DRM_ERROR("Failed to disable pipe\n");
if (IS_MOFD(dev)) {
/*
* FIXME: turn off the power island directly
* although failed to disable pipe.
*/
err = 0;
} else
err = -EAGAIN;
goto power_off_err;
}
}
if (!is_dual_dsi(dev)) {
/*enter ULPS*/
__dbi_enter_ulps_locked(dsi_config, offset);
} else {
/*Disable MIPI port*/
REG_WRITE(regs->mipi_reg, (REG_READ(regs->mipi_reg) & ~BIT31));
/*clear Low power output hold*/
REG_WRITE(regs->mipi_reg, (REG_READ(regs->mipi_reg) & ~BIT16));
/*Disable DSI controller*/
REG_WRITE(regs->device_ready_reg, (ctx->device_ready & ~BIT0));
/*enter ULPS*/
__dbi_enter_ulps_locked(dsi_config, offset);
offset = 0x1000;
/*Disable MIPI port*/
REG_WRITE(regs->mipi_reg +offset,
(REG_READ(regs->mipi_reg + offset) & ~BIT31));
/*clear Low power output hold*/
REG_WRITE(regs->mipi_reg + offset,
(REG_READ(regs->mipi_reg + offset) & ~BIT16));
offset = 0x800;
/*Disable DSI controller*/
REG_WRITE(regs->device_ready_reg + offset, (ctx->device_ready & ~BIT0));
/*enter ULPS*/
__dbi_enter_ulps_locked(dsi_config, offset);
offset = 0x0;
}
power_off_err:
power_island = pipe_to_island(dsi_config->pipe);
if (power_island & (OSPM_DISPLAY_A | OSPM_DISPLAY_C))
power_island |= OSPM_DISPLAY_MIO;
if (is_dual_dsi(dev))
power_island |= OSPM_DISPLAY_C;
if (!power_island_put(power_island))
return -EINVAL;
return err;
}
/**
* Power on sequence for video mode MIPI panel.
* NOTE: do NOT modify this function
*/
static int __dpi_panel_power_on(struct mdfld_dsi_config *dsi_config,
struct panel_funcs *p_funcs)
{
u32 val = 0;
struct mdfld_dsi_hw_registers *regs;
struct mdfld_dsi_hw_context *ctx;
struct drm_psb_private *dev_priv;
struct drm_device *dev;
int retry, reset_count = 10;
int i;
int err = 0;
u32 guit_val = 0;
u32 power_island = 0;
int offset = 0;
PSB_DEBUG_ENTRY("\n");
if (!dsi_config)
return -EINVAL;
regs = &dsi_config->regs;
ctx = &dsi_config->dsi_hw_context;
dev = dsi_config->dev;
dev_priv = dev->dev_private;
power_island = pipe_to_island(dsi_config->pipe);
if (power_island & (OSPM_DISPLAY_A | OSPM_DISPLAY_C))
power_island |= OSPM_DISPLAY_MIO;
if (is_dual_dsi(dev))
power_island |= OSPM_DISPLAY_C;
if (!power_island_get(power_island))
return -EAGAIN;
reset_recovery:
--reset_count;
/*HW-Reset*/
if (p_funcs && p_funcs->reset)
p_funcs->reset(dsi_config);
/*
* Wait for DSI PLL locked on pipe, and only need to poll status of pipe
* A as both MIPI pipes share the same DSI PLL.
*/
if (dsi_config->pipe == 0) {
retry = 20000;
while (!(REG_READ(regs->pipeconf_reg) & PIPECONF_DSIPLL_LOCK) &&
--retry)
udelay(150);
if (!retry) {
DRM_ERROR("PLL failed to lock on pipe\n");
err = -EAGAIN;
goto power_on_err;
}
}
if (IS_ANN_A0(dev)) {
/* FIXME: reset the DC registers for ANN A0 */
power_island_get(OSPM_DISPLAY_B | OSPM_DISPLAY_C);
REG_WRITE(DSPCLK_GATE_D, 0xFFFFFFFF); /* 0x10000000 */
REG_WRITE(RAMCLK_GATE_D, 0xFFFFFFFF); /* 0x0 */
REG_WRITE(PFIT_CONTROL, 0x20000000);
REG_WRITE(DSPIEDCFGSHDW, 0x0);
REG_WRITE(DSPARB2, 0x000A0200);
REG_WRITE(DSPARB, 0x18040080);
REG_WRITE(DSPFW1, 0x0F0F3F3F);
REG_WRITE(DSPFW2, 0x5F2F0F3F);
REG_WRITE(DSPFW3, 0x0);
REG_WRITE(DSPFW4, 0x07071F1F);
REG_WRITE(DSPFW5, 0x2F17071F);
REG_WRITE(DSPFW6, 0x00001F3F);
REG_WRITE(DSPFW7, 0x1F3F1F3F);
REG_WRITE(DSPSRCTRL, 0x00080100);
REG_WRITE(DSPCHICKENBIT, 0x0);
REG_WRITE(FBDC_CHICKEN, 0x0C0C0C0C);
REG_WRITE(CURACNTR, 0x0);
REG_WRITE(CURBCNTR, 0x0);
REG_WRITE(CURCCNTR, 0x0);
REG_WRITE(IEP_OVA_CTRL, 0x0);
REG_WRITE(IEP_OVA_CTRL, 0x0);
REG_WRITE(DSPACNTR, 0x0);
REG_WRITE(DSPBCNTR, 0x0);
REG_WRITE(DSPCCNTR, 0x0);
REG_WRITE(DSPDCNTR, 0x0);
REG_WRITE(DSPECNTR, 0x0);
REG_WRITE(DSPFCNTR, 0x0);
power_island_put(OSPM_DISPLAY_B | OSPM_DISPLAY_C);
}
__dpi_set_properties(dsi_config, PORT_A);
/*Setup pipe timing*/
REG_WRITE(regs->htotal_reg, ctx->htotal);
REG_WRITE(regs->hblank_reg, ctx->hblank);
REG_WRITE(regs->hsync_reg, ctx->hsync);
REG_WRITE(regs->vtotal_reg, ctx->vtotal);
REG_WRITE(regs->vblank_reg, ctx->vblank);
REG_WRITE(regs->vsync_reg, ctx->vsync);
REG_WRITE(regs->pipesrc_reg, ctx->pipesrc);
REG_WRITE(regs->dsppos_reg, ctx->dsppos);
REG_WRITE(regs->dspstride_reg, ctx->dspstride);
/*Setup plane*/
REG_WRITE(regs->dspsize_reg, ctx->dspsize);
REG_WRITE(regs->dspsurf_reg, ctx->dspsurf);
REG_WRITE(regs->dsplinoff_reg, ctx->dsplinoff);
REG_WRITE(regs->vgacntr_reg, ctx->vgacntr);
/*restore color_coef (chrome) */
for (i = 0; i < 6; i++)
REG_WRITE(regs->color_coef_reg + (i<<2), ctx->color_coef[i]);
/* restore palette (gamma) */
for (i = 0; i < 256; i++)
REG_WRITE(regs->palette_reg + (i<<2), ctx->palette[i]);
/* restore dpst setting */
if (dev_priv->psb_dpst_state) {
dpstmgr_reg_restore_locked(dev, dsi_config);
psb_enable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
}
if (__dpi_config_port(dsi_config, p_funcs, PORT_A) != 0) {
if (!reset_count) {
err = -EAGAIN;
goto power_on_err;
}
DRM_ERROR("Failed to init dsi controller, reset it!\n");
goto reset_recovery;
}
if (is_dual_dsi(dev)) {
__dpi_set_properties(dsi_config, PORT_C);
__dpi_config_port(dsi_config, p_funcs, PORT_C);
}
/**
* Different panel may have different ways to have
* drvIC initialized. Support it!
*/
if (p_funcs && p_funcs->drv_ic_init) {
if (p_funcs->drv_ic_init(dsi_config)) {
if (!reset_count) {
err = -EAGAIN;
goto power_on_err;
}
DRM_ERROR("Failed to init dsi controller, reset it!\n");
goto reset_recovery;
}
}
/*Enable MIPI Port A*/
offset = 0x0;
REG_WRITE(regs->mipi_reg + offset, (ctx->mipi | BIT31));
REG_WRITE(regs->dpi_control_reg + offset, BIT1);
if (is_dual_dsi(dev)) {
/*Enable MIPI Port C*/
offset = 0x1000;
REG_WRITE(regs->mipi_reg + offset, (ctx->mipi | BIT31));
offset = 0x800;
REG_WRITE(regs->dpi_control_reg + offset, BIT1);
}
/**
* Different panel may have different ways to have
* panel turned on. Support it!
*/
if (p_funcs && p_funcs->power_on)
if (p_funcs->power_on(dsi_config)) {
DRM_ERROR("Failed to power on panel\n");
err = -EAGAIN;
goto power_on_err;
}
if (IS_ANN_A0(dev)) {
REG_WRITE(regs->ddl1_reg, ctx->ddl1);
REG_WRITE(regs->ddl2_reg, ctx->ddl2);
REG_WRITE(regs->ddl3_reg, ctx->ddl3);
REG_WRITE(regs->ddl4_reg, ctx->ddl4);
}
/*Enable pipe*/
val = ctx->pipeconf;
val &= ~0x000c0000;
/**
* Frame Start occurs on third HBLANK
* after the start of VBLANK
*/
val |= BIT31 | BIT28;
REG_WRITE(regs->pipeconf_reg, val);
/*Wait for pipe enabling,when timing generator
is wroking */
if (REG_READ(regs->mipi_reg) & BIT31) {
retry = 10000;
while (--retry && !(REG_READ(regs->pipeconf_reg) & BIT30))
udelay(3);
if (!retry) {
DRM_ERROR("Failed to enable pipe\n");
err = -EAGAIN;
goto power_on_err;
}
}
/*enable plane*/
val = ctx->dspcntr | BIT31;
REG_WRITE(regs->dspcntr_reg, val);
if (p_funcs && p_funcs->set_brightness) {
if (p_funcs->set_brightness(dsi_config,
ctx->lastbrightnesslevel))
DRM_ERROR("Failed to set panel brightness\n");
} else {
DRM_ERROR("Failed to set panel brightness\n");
}
if (p_funcs && p_funcs->drv_set_panel_mode)
p_funcs->drv_set_panel_mode(dsi_config);
psb_enable_vblank(dev, dsi_config->pipe);
return err;
power_on_err:
power_island_put(power_island);
return err;
}
bool enable_DSIPLL(struct drm_device *dev)
{
DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
struct mdfld_dsi_config *dsi_config = NULL;
struct mdfld_dsi_hw_context *ctx = NULL;
u32 guit_val = 0x0;
u32 retry;
if (!dev_priv)
goto err_out;
dsi_config = dev_priv->dsi_configs[0];
if (!dsi_config)
goto err_out;
ctx = &dsi_config->dsi_hw_context;
/*TODO: vcheeram : Remove the hardcoding of the register*/
if (is_dual_dsi(dev))
intel_mid_msgbus_write32(CCK_PORT,
FUSE_OVERRIDE_FREQ_CNTRL_REG5, 0x682);
/* Prepare DSI PLL register before enabling */
intel_mid_msgbus_write32(CCK_PORT, DSI_PLL_DIV_REG, 0);
guit_val = intel_mid_msgbus_read32(CCK_PORT, DSI_PLL_CTRL_REG);
guit_val &= ~(DPLL_VCO_ENABLE | _DSI_LDO_EN
|_CLK_EN_MASK | _DSI_MUX_SEL_CCK_DSI0 | _DSI_MUX_SEL_CCK_DSI1);
intel_mid_msgbus_write32(CCK_PORT,
DSI_PLL_CTRL_REG, guit_val);
udelay(1);
/* Program PLL */
/*first set up the dpll and fp variables
* dpll - will contain the following information
* - the clock source - DSI vs HFH vs LFH PLL
* - what clocks should be running DSI0, DSI1
* - and the divisor.
*
*/
intel_mid_msgbus_write32(CCK_PORT, DSI_PLL_DIV_REG, ctx->fp);
guit_val &= ~_P1_POST_DIV_MASK; /*clear the divisor bit*/
/* the ctx->dpll contains the divisor that we need to use as well as which clocks
* need to start up */
guit_val |= ctx->dpll;
guit_val &= ~_DSI_LDO_EN; /* We want to clear the LDO enable when programming*/
guit_val |= DPLL_VCO_ENABLE; /* Enable the DSI PLL */
/* For the CD clock (clock used by Display controller), we need to set
* the DSI_CCK_PLL_SELECT bit (bit 11). This should already be set. But
* setting it just in case
*/
if (dev_priv->bUseHFPLL)
guit_val |= _DSI_CCK_PLL_SELECT;
intel_mid_msgbus_write32(CCK_PORT, DSI_PLL_CTRL_REG, guit_val);
/* Wait for DSI PLL lock */
retry = 10000;
guit_val = intel_mid_msgbus_read32(CCK_PORT, DSI_PLL_CTRL_REG);
while (((guit_val & _DSI_PLL_LOCK) != _DSI_PLL_LOCK) && (--retry)) {
udelay(3);
guit_val = intel_mid_msgbus_read32(CCK_PORT, DSI_PLL_CTRL_REG);
if (!retry%1000)
DRM_ERROR("DSI PLL taking too long to lock"
"- retry count=%d\n", 10000-retry);
}
if (retry == 0) {
DRM_ERROR("DSI PLL fails to lock\n");
return false;
}
return true;
err_out:
return false;
}
