static void setenv_fdt_file(void) { const char *cmp_dtb = CONFIG_DEFAULT_DEVICE_TREE; if (!strcmp(cmp_dtb, "imx6q-icore")) { if (is_mx6dq()) env_set("fdt_file", "imx6q-icore.dtb"); else if (is_mx6dl() || is_mx6solo()) env_set("fdt_file", "imx6dl-icore.dtb"); } else if (!strcmp(cmp_dtb, "imx6q-icore-mipi")) { if (is_mx6dq()) env_set("fdt_file", "imx6q-icore-mipi.dtb"); else if (is_mx6dl() || is_mx6solo()) env_set("fdt_file", "imx6dl-icore-mipi.dtb"); } else if (!strcmp(cmp_dtb, "imx6q-icore-rqs")) { if (is_mx6dq()) env_set("fdt_file", "imx6q-icore-rqs.dtb"); else if (is_mx6dl() || is_mx6solo()) env_set("fdt_file", "imx6dl-icore-rqs.dtb"); } else if (!strcmp(cmp_dtb, "imx6ul-geam-kit")) env_set("fdt_file", "imx6ul-geam-kit.dtb"); else if (!strcmp(cmp_dtb, "imx6ul-isiot-mmc")) env_set("fdt_file", "imx6ul-isiot-emmc.dtb"); else if (!strcmp(cmp_dtb, "imx6ul-isiot-emmc")) env_set("fdt_file", "imx6ul-isiot-emmc.dtb"); else if (!strcmp(cmp_dtb, "imx6ul-isiot-nand")) env_set("fdt_file", "imx6ul-isiot-nand.dtb"); }
void setenv_fdt_file(void) { if (is_mx6dq()) setenv("fdt_file", "imx6q-icore.dtb"); else if(is_mx6dl() || is_mx6solo()) setenv("fdt_file", "imx6dl-icore.dtb"); }
int board_fit_config_name_match(const char *name) { if (is_mx6dq() && !strcmp(name, "imx6q-icore")) return 0; else if (is_mx6dq() && !strcmp(name, "imx6q-icore-rqs")) return 0; else if (is_mx6dq() && !strcmp(name, "imx6q-icore-mipi")) return 0; else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore")) return 0; else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore-rqs")) return 0; else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore-mipi")) return 0; else return -1; }
static void spl_dram_init(void) { #ifdef CONFIG_MX6QDL if (is_mx6solo()) { mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256); } else if (is_mx6dl()) { mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256); } else if (is_mx6dq()) { mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256); } #elif CONFIG_MX6UL mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); #endif udelay(100); }