static Uart*
uartisapnp(void)
{
int ctlrno;
ISAConf isa;
Uart *head, *tail, *uart;
/*
* Look for up to 4 discrete UARTs on the ISA bus.
* All suitable devices are configured to simply point
* to the generic i8250 driver.
*/
head = tail = nil;
for(ctlrno = 2; ctlrno < 6; ctlrno++) {
memset(&isa, 0, sizeof(isa));
if(!isaconfig("uart", ctlrno, &isa))
continue;
if(strcmp(isa.type, "isa") != 0)
continue;
if(isa.port == 0 || isa.irq == 0)
continue;
if(isa.freq == 0)
isa.freq = 1843200;
uart = uartisa(ctlrno, &isa);
if(uart == nil)
continue;
if(head != nil)
tail->next = uart;
else
head = uart;
tail = uart;
}
return head;
}
int
etherinit(void)
{
Ctlr *ctlr;
int ctlrno, i, mask, n;
mask = 0;
for(ctlrno = 0; ctlrno < MaxEther; ctlrno++){
ctlr = ðer[ctlrno];
memset(ctlr, 0, sizeof(Ctlr));
if(isaconfig("ether", ctlrno, &ctlr->card) == 0)
continue;
for(n = 0; cards[n].type; n++){
if(strcmp(cards[n].type, ctlr->card.type))
continue;
ctlr->ctlrno = ctlrno;
if((*cards[n].reset)(ctlr))
break;
ctlr->iq = qopen(16*1024, 1, 0, 0);
ctlr->oq = qopen(16*1024, 1, 0, 0);
ctlr->present = 1;
mask |= 1<<ctlrno;
print("ether%d: %s: port 0x%luX irq %d",
ctlr->ctlrno, ctlr->card.type, ctlr->card.port, ctlr->card.irq);
if(ctlr->card.mem)
print(" addr 0x%luX", ctlr->card.mem & ~KZERO);
if(ctlr->card.size)
print(" size 0x%luX", ctlr->card.size);
print(":");
for(i = 0; i < sizeof(ctlr->card.ea); i++)
print(" %2.2uX", ctlr->card.ea[i]);
print("\n"); uartwait();
setvec(ctlr->card.irq, ctlr->card.intr, ctlr);
break;
}
}
return mask;
}
int
etherinit(void)
{
Ether *ctlr;
int ctlrno, i, mask, n, x;
fmtinstall('E', eipfmt);
if (getconf("*fakeintrs") != nil || getconf("*9loadfakeintrs") != nil)
startfakeintrs();
etherdetach = xetherdetach;
mask = 0;
for(ctlrno = 0; ctlrno < MaxEther; ctlrno++){
ctlr = ðer[ctlrno];
memset(ctlr, 0, sizeof(Ether));
if(iniread && isaconfig("ether", ctlrno, ctlr) == 0)
continue;
for(n = 0; ethercards[n].type; n++){
if(!iniread){
if(ethercards[n].noprobe)
continue;
memset(ctlr, 0, sizeof(Ether));
strcpy(ctlr->type, ethercards[n].type);
}
else if(cistrcmp(ethercards[n].type, ctlr->type))
continue;
ctlr->ctlrno = ctlrno;
x = splhi();
if((*ethercards[n].reset)(ctlr)){
splx(x);
if(iniread)
break;
else
continue;
}
ctlr->state = 1; /* card found */
mask |= 1<<ctlrno;
if(ctlr->irq == 2)
ctlr->irq = 9;
setvec(VectorPIC + ctlr->irq, ctlr->interrupt, ctlr);
print("ether#%d: %s: port 0x%luX irq %lud",
ctlr->ctlrno, ctlr->type, ctlr->port, ctlr->irq);
if(ctlr->mem)
print(" addr 0x%luX", ctlr->mem & ~KZERO);
if(ctlr->size)
print(" size 0x%luX", ctlr->size);
print(": %E\n", ctlr->ea);
if(ctlr->nrb == 0)
ctlr->nrb = Nrb;
ctlr->rb = ialloc(sizeof(RingBuf)*ctlr->nrb, 0);
if(ctlr->ntb == 0)
ctlr->ntb = Ntb;
ctlr->tb = ialloc(sizeof(RingBuf)*ctlr->ntb, 0);
ctlr->rh = 0;
ctlr->ri = 0;
for(i = 0; i < ctlr->nrb; i++)
ctlr->rb[i].owner = Interface;
ctlr->th = 0;
ctlr->ti = 0;
for(i = 0; i < ctlr->ntb; i++)
ctlr->tb[i].owner = Host;
splx(x);
break;
}
}
if (mask == 0) {
print("no ethernet interfaces recognised\n");
pcihinv(nil, Pcibcnet);
}
return mask;
}
static I82365*
i82365probe(int x, int d, int dev)
{
uchar c, id;
I82365 *cp;
ISAConf isa;
int i, nslot;
outb(x, Rid + (dev<<7));
id = inb(d);
if((id & 0xf0) != 0x80)
return 0; /* not a memory & I/O card */
if((id & 0x0f) == 0x00)
return 0; /* no revision number, not possible */
cp = xalloc(sizeof(I82365));
cp->xreg = x;
cp->dreg = d;
cp->dev = dev;
cp->type = Ti82365;
cp->nslot = 2;
switch(id){
case 0x82:
case 0x83:
case 0x84:
/* could be a cirrus */
outb(x, Rchipinfo + (dev<<7));
outb(d, 0);
c = inb(d);
if((c & 0xc0) != 0xc0)
break;
c = inb(d);
if((c & 0xc0) != 0x00)
break;
if(c & 0x20){
cp->type = Tpd6720;
} else {
cp->type = Tpd6710;
cp->nslot = 1;
}
/* low power mode */
outb(x, Rmisc2 + (dev<<7));
c = inb(d);
outb(d, c & ~Flowpow);
break;
}
/* if it's not a Cirrus, it could be a Vadem... */
if(cp->type == Ti82365){
/* unlock the Vadem extended regs */
outb(x, 0x0E + (dev<<7));
outb(x, 0x37 + (dev<<7));
/* make the id register show the Vadem id */
outb(x, 0x3A + (dev<<7));
c = inb(d);
outb(d, c|0xC0);
outb(x, Rid + (dev<<7));
c = inb(d);
if(c & 0x08)
cp->type = Tvg46x;
/* go back to Intel compatible id */
outb(x, 0x3A + (dev<<7));
c = inb(d);
outb(d, c & ~0xC0);
}
memset(&isa, 0, sizeof(ISAConf));
if(isaconfig("pcmcia", ncontroller, &isa) && isa.irq)
cp->irq = isa.irq;
else
cp->irq = IrqPCMCIA;
for(i = 0; i < isa.nopt; i++){
if(cistrncmp(isa.opt[i], "nslot=", 6))
continue;
nslot = strtol(&isa.opt[i][6], nil, 0);
if(nslot > 0 && nslot <= 2)
cp->nslot = nslot;
}
controller[ncontroller++] = cp;
return cp;
}
