void tic_init() { tic_msec = 0; // Setup timer0.0 timer0->compare0 = (FCPU/10000); timer0->counter0 = 0; timer0->tcr0 = TIMER_EN | TIMER_AR | TIMER_IRQEN; isr_register(1, &tic_isr); }
void pit_init(void) { isr_register(IRQ0, &pit_handler); uint32_t di = 1193180 / pit_hz; uint8_t lo = (uint8_t)(di & 0xFF); uint8_t hi = (uint8_t)((di >> 8) & 0xFF); outb(0x43, 0x36); /* Change the PIT */ outb(0x40, lo); outb(0x40, hi); }
int kstart(int code, multiboot_info_t * mBootInfo) { isr_register(0xD, gp_handler); if (code != MULTIBOOT_BOOTLOADER_MAGIC) { PANIC("Kernel need to be loaded by a multiboot" " compliant bootloader\n"); } printk("Kernel up and running\n"); return 0xDEAD; }
void tic_init() //Inicialización de el timer { // Set high M1,M2,M3 and M4 gpio0->out=0x0F; // Setup timer0.0 timer0->compare0 = set_period(); timer0->counter0 = 0; timer0->tcr0 = TIMER_EN | TIMER_AR | TIMER_IRQEN; // Setup timer0.1 timer0->compare1 = set_duty(pwm_d[0]); timer0->counter1 = 0; timer0->tcr1 = TIMER_EN | TIMER_AR | TIMER_IRQEN; // Setup timer0.2 timer0->compare2 = set_period(); timer0->counter2 = 0; timer0->tcr2 = TIMER_EN | TIMER_AR | TIMER_IRQEN; // Setup timer0.3 timer0->compare3 = set_duty(pwm_d[1]); timer0->counter3 = 0; timer0->tcr3 = TIMER_EN | TIMER_AR | TIMER_IRQEN; // Setup timer0.4 timer0->compare4 = set_period(); timer0->counter4 = 0; timer0->tcr4 = TIMER_EN | TIMER_AR | TIMER_IRQEN; // Setup timer0.5 timer0->compare5 = set_duty(pwm_d[2]); timer0->counter5 = 0; timer0->tcr5 = TIMER_EN | TIMER_AR | TIMER_IRQEN; // Setup timer0.6 timer0->compare6 = set_period(); timer0->counter6 = 0; timer0->tcr6 = TIMER_EN | TIMER_AR | TIMER_IRQEN; // Setup timer0.7 timer0->compare7 = set_duty(pwm_d[3]); timer0->counter7 = 0; timer0->tcr7 = TIMER_EN | TIMER_AR | TIMER_IRQEN; isr_register(3, &tic_isr_0); isr_register(4, &tic_isr_1); isr_register(5, &tic_isr_2); isr_register(6, &tic_isr_3); isr_register(7, &tic_isr_4); isr_register(8, &tic_isr_5); isr_register(9, &tic_isr_6); isr_register(10, &tic_isr_7); //Button function register isr_register(15, &tic_isr_15); isr_register(16, &tic_isr_16); isr_register(17, &tic_isr_17); isr_register(18, &tic_isr_18); isr_register(19, &tic_isr_19); }