static int iss_isp_reset(struct iss_device *iss) { unsigned int timeout; /* Fist, ensure that the ISP is IDLE (no transactions happening) */ iss_reg_update(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_SYSCONFIG, ISP5_SYSCONFIG_STANDBYMODE_MASK, ISP5_SYSCONFIG_STANDBYMODE_SMART); iss_reg_set(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_CTRL, ISP5_CTRL_MSTANDBY); timeout = iss_poll_condition_timeout( iss_reg_read(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_CTRL) & ISP5_CTRL_MSTANDBY_WAIT, 1000000, 1000, 1500); if (timeout) { dev_err(iss->dev, "ISP5 standby timeout\n"); return -ETIMEDOUT; } /* Now finally, do the reset */ iss_reg_set(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_SYSCONFIG, ISP5_SYSCONFIG_SOFTRESET); timeout = iss_poll_condition_timeout( !(iss_reg_read(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_SYSCONFIG) & ISP5_SYSCONFIG_SOFTRESET), 1000000, 1000, 1500); if (timeout) { dev_err(iss->dev, "ISP5 reset timeout\n"); return -ETIMEDOUT; } return 0; }
/* * omap4iss_csi2_reset - Resets the CSI2 module. * * Must be called with the phy lock held. * * Returns 0 if successful, or -EBUSY if power command didn't respond. */ int omap4iss_csi2_reset(struct iss_csi2_device *csi2) { unsigned int timeout; if (!csi2->available) return -ENODEV; if (csi2->phy->phy_in_use) return -EBUSY; iss_reg_set(csi2->iss, csi2->regs1, CSI2_SYSCONFIG, CSI2_SYSCONFIG_SOFT_RESET); timeout = iss_poll_condition_timeout( iss_reg_read(csi2->iss, csi2->regs1, CSI2_SYSSTATUS) & CSI2_SYSSTATUS_RESET_DONE, 500, 100, 200); if (timeout) { dev_err(csi2->iss->dev, "CSI2: Soft reset timeout!\n"); return -EBUSY; } iss_reg_set(csi2->iss, csi2->regs1, CSI2_COMPLEXIO_CFG, CSI2_COMPLEXIO_CFG_RESET_CTRL); timeout = iss_poll_condition_timeout( iss_reg_read(csi2->iss, csi2->phy->phy_regs, REGISTER1) & REGISTER1_RESET_DONE_CTRLCLK, 10000, 100, 500); if (timeout) { dev_err(csi2->iss->dev, "CSI2: CSI2_96M_FCLK reset timeout!\n"); return -EBUSY; } iss_reg_update(csi2->iss, csi2->regs1, CSI2_SYSCONFIG, CSI2_SYSCONFIG_MSTANDBY_MODE_MASK | CSI2_SYSCONFIG_AUTO_IDLE, CSI2_SYSCONFIG_MSTANDBY_MODE_NO); return 0; }
/* * csi2_irq_status_set - Enables CSI2 Status IRQs. * @enable: Enable/disable CSI2 Status interrupts */ static void csi2_irq_status_set(struct iss_csi2_device *csi2, int enable) { u32 reg; reg = CSI2_IRQ_OCP_ERR | CSI2_IRQ_SHORT_PACKET | CSI2_IRQ_ECC_CORRECTION | CSI2_IRQ_ECC_NO_CORRECTION | CSI2_IRQ_COMPLEXIO_ERR | CSI2_IRQ_FIFO_OVF | CSI2_IRQ_CONTEXT0; iss_reg_write(csi2->iss, csi2->regs1, CSI2_IRQSTATUS, reg); if (enable) iss_reg_set(csi2->iss, csi2->regs1, CSI2_IRQENABLE, reg); else iss_reg_write(csi2->iss, csi2->regs1, CSI2_IRQENABLE, 0); }
static int iss_reset(struct iss_device *iss) { unsigned int timeout; iss_reg_set(iss, OMAP4_ISS_MEM_TOP, ISS_HL_SYSCONFIG, ISS_HL_SYSCONFIG_SOFTRESET); timeout = iss_poll_condition_timeout( !(iss_reg_read(iss, OMAP4_ISS_MEM_TOP, ISS_HL_SYSCONFIG) & ISS_HL_SYSCONFIG_SOFTRESET), 1000, 10, 100); if (timeout) { dev_err(iss->dev, "ISS reset timeout\n"); return -ETIMEDOUT; } iss->crashed = 0; return 0; }
/* * csi2_irq_ctx_set - Enables CSI2 Context IRQs. * @enable: Enable/disable CSI2 Context interrupts */ static void csi2_irq_ctx_set(struct iss_csi2_device *csi2, int enable) { u32 reg = CSI2_CTX_IRQ_FE; int i; if (csi2->use_fs_irq) reg |= CSI2_CTX_IRQ_FS; for (i = 0; i < 8; i++) { iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_IRQSTATUS(i), reg); if (enable) iss_reg_set(csi2->iss, csi2->regs1, CSI2_CTX_IRQENABLE(i), reg); else iss_reg_clr(csi2->iss, csi2->regs1, CSI2_CTX_IRQENABLE(i), reg); } }
/* * csi2_irq_complexio1_set - Enables CSI2 ComplexIO IRQs. * @enable: Enable/disable CSI2 ComplexIO #1 interrupts */ static void csi2_irq_complexio1_set(struct iss_csi2_device *csi2, int enable) { u32 reg; reg = CSI2_COMPLEXIO_IRQ_STATEALLULPMEXIT | CSI2_COMPLEXIO_IRQ_STATEALLULPMENTER | CSI2_COMPLEXIO_IRQ_STATEULPM5 | CSI2_COMPLEXIO_IRQ_ERRCONTROL5 | CSI2_COMPLEXIO_IRQ_ERRESC5 | CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS5 | CSI2_COMPLEXIO_IRQ_ERRSOTHS5 | CSI2_COMPLEXIO_IRQ_STATEULPM4 | CSI2_COMPLEXIO_IRQ_ERRCONTROL4 | CSI2_COMPLEXIO_IRQ_ERRESC4 | CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS4 | CSI2_COMPLEXIO_IRQ_ERRSOTHS4 | CSI2_COMPLEXIO_IRQ_STATEULPM3 | CSI2_COMPLEXIO_IRQ_ERRCONTROL3 | CSI2_COMPLEXIO_IRQ_ERRESC3 | CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS3 | CSI2_COMPLEXIO_IRQ_ERRSOTHS3 | CSI2_COMPLEXIO_IRQ_STATEULPM2 | CSI2_COMPLEXIO_IRQ_ERRCONTROL2 | CSI2_COMPLEXIO_IRQ_ERRESC2 | CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS2 | CSI2_COMPLEXIO_IRQ_ERRSOTHS2 | CSI2_COMPLEXIO_IRQ_STATEULPM1 | CSI2_COMPLEXIO_IRQ_ERRCONTROL1 | CSI2_COMPLEXIO_IRQ_ERRESC1 | CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS1 | CSI2_COMPLEXIO_IRQ_ERRSOTHS1; iss_reg_write(csi2->iss, csi2->regs1, CSI2_COMPLEXIO_IRQSTATUS, reg); if (enable) iss_reg_set(csi2->iss, csi2->regs1, CSI2_COMPLEXIO_IRQENABLE, reg); else iss_reg_write(csi2->iss, csi2->regs1, CSI2_COMPLEXIO_IRQENABLE, 0); }