/*
* Check to see if the real expression is of the form (expr) * <scale>
*/
static unsigned check_scaled_real_expr(ivl_expr_t expr, double scale)
{
double scale_val;
if ((ivl_expr_type(expr) != IVL_EX_BINARY) ||
(ivl_expr_opcode(expr) != '*') ||
(ivl_expr_type(ivl_expr_oper2(expr)) != IVL_EX_REALNUM)) {
fprintf(stderr, "%s:%u: vlog95 error: Variable real time unit "
" expression/value cannot be scaled.\n ",
ivl_expr_file(expr), ivl_expr_lineno(expr));
vlog_errors += 1;
return 0;
}
scale_val = ivl_expr_dvalue(ivl_expr_oper2(expr));
if (scale != scale_val) {
fprintf(stderr, "%s:%u: vlog95 error: Variable real time unit "
"expression/value scale coefficient did not "
"match expected value (%g != %g).\n",
ivl_expr_file(expr), ivl_expr_lineno(expr),
scale, scale_val);
vlog_errors += 1;
return 0;
}
/* Yes, this expression is of the correct form. */
return 1;
}
// HERE: Probably need to pass in a msg string to make this work with
// indexed part selects.
static unsigned is_scaled_expr(ivl_expr_t expr, int msb, int lsb)
{
int64_t scale_val;
int rtype;
/* This is as easy as removing the addition/subtraction that was
* added to scale the value to be zero based, but we need to verify
* that the scaling value is correct first. */
if (msb > lsb) {
if ((ivl_expr_type(expr) != IVL_EX_BINARY) ||
((ivl_expr_opcode(expr) != '+') &&
(ivl_expr_opcode(expr) != '-')) ||
(ivl_expr_type(ivl_expr_oper2(expr)) != IVL_EX_NUMBER)) {
fprintf(vlog_out, "<invalid>");
fprintf(stderr, "%s:%u: vlog95 error: Scaled "
"expression value cannot be scaled.\n",
ivl_expr_file(expr),
ivl_expr_lineno(expr));
vlog_errors += 1;
return 0;
}
scale_val = get_valid_int64_from_number(
ivl_expr_oper2(expr), &rtype,
"expression value scale coefficient");
} else {
if ((ivl_expr_type(expr) != IVL_EX_BINARY) ||
((ivl_expr_opcode(expr) != '+') &&
(ivl_expr_opcode(expr) != '-')) ||
(ivl_expr_type(ivl_expr_oper1(expr)) != IVL_EX_NUMBER)) {
fprintf(vlog_out, "<invalid>");
fprintf(stderr, "%s:%u: vlog95 error: Scaled "
"expression value cannot be scaled.\n",
ivl_expr_file(expr),
ivl_expr_lineno(expr));
vlog_errors += 1;
return 0;
}
scale_val = get_valid_int64_from_number(
ivl_expr_oper1(expr), &rtype,
"expression value scale coefficient");
}
if (rtype) return 0;
if (ivl_expr_opcode(expr) == '+') scale_val *= -1;
if (lsb != scale_val) {
fprintf(vlog_out, "<invalid>");
fprintf(stderr, "%s:%u: vlog95 error: Scaled expression value "
"scaling coefficient did not match expected "
"value (%d != %"PRIu64").\n",
ivl_expr_file(expr), ivl_expr_lineno(expr),
lsb, scale_val);
vlog_errors += 1;
return 0;
}
return 1;
}
static void draw_binary_vec4_lrs(ivl_expr_t expr)
{
ivl_expr_t le = ivl_expr_oper1(expr);
ivl_expr_t re = ivl_expr_oper2(expr);
// Push the left expression onto the stack.
draw_eval_vec4(le);
// Calculate the shift amount into an index register.
int use_index_reg = allocate_word();
assert(use_index_reg >= 0);
draw_eval_expr_into_integer(re, use_index_reg);
// Emit the actual shift instruction. This will pop the top of
// the stack and replace it with the result of the shift.
switch (ivl_expr_opcode(expr)) {
case 'l': /* << */
fprintf(vvp_out, " %%shiftl %d;\n", use_index_reg);
break;
case 'r': /* >> */
fprintf(vvp_out, " %%shiftr %d;\n", use_index_reg);
break;
case 'R': /* >>> */
if (ivl_expr_signed(le))
fprintf(vvp_out, " %%shiftr/s %d;\n", use_index_reg);
else
fprintf(vvp_out, " %%shiftr %d;\n", use_index_reg);
break;
default:
assert(0);
break;
}
clr_word(use_index_reg);
}
void emit_scaled_expr(ivl_scope_t scope, ivl_expr_t expr, int msb, int lsb)
{
if (msb >= lsb) {
if (ivl_expr_type(expr) == IVL_EX_NUMBER) {
int rtype;
int64_t value = get_valid_int64_from_number(expr, &rtype,
"value");
if (rtype) return;
value += lsb;
fprintf(vlog_out, "%"PRId64, value);
} else if (lsb == 0) {
/* If the LSB is zero then there is no scale. */
emit_expr(scope, expr, 0);
} else {
if (is_scaled_expr(expr, msb, lsb)) {
emit_expr(scope, ivl_expr_oper1(expr), 0);
}
}
} else {
if (ivl_expr_type(expr) == IVL_EX_NUMBER) {
int rtype;
int64_t value = get_valid_int64_from_number(expr, &rtype,
"value");
if (rtype) return;
value = (int64_t)lsb - value;
fprintf(vlog_out, "%"PRId64, value);
} else {
if (is_scaled_expr(expr, msb, lsb)) {
emit_expr(scope, ivl_expr_oper2(expr), 0);
}
}
}
}
static void draw_binary_vec4_bitwise(ivl_expr_t expr)
{
draw_eval_vec4(ivl_expr_oper1(expr));
draw_eval_vec4(ivl_expr_oper2(expr));
switch (ivl_expr_opcode(expr)) {
case '&':
fprintf(vvp_out, " %%and;\n");
break;
case '|':
fprintf(vvp_out, " %%or;\n");
break;
case '^':
fprintf(vvp_out, " %%xor;\n");
break;
case 'A': /* ~& */
fprintf(vvp_out, " %%nand;\n");
break;
case 'O': /* ~| */
fprintf(vvp_out, " %%nor;\n");
break;
case 'X': /* ~^ */
fprintf(vvp_out, " %%xnor;\n");
break;
default:
assert(0);
break;
}
}
/*
* Check to see if the statement R-value is a port in the given scope.
* If it is return the zero based port number.
*/
static unsigned utask_out_port_idx(ivl_scope_t scope, ivl_statement_t stmt)
{
unsigned idx, ports = ivl_scope_ports(scope);
ivl_expr_t rval = ivl_stmt_rval(stmt);
ivl_signal_t rsig = 0;
ivl_expr_type_t expr_type = ivl_expr_type(rval);
const char *sig_name;
/* We can have a simple signal. */
if (expr_type == IVL_EX_SIGNAL) {
rsig = ivl_expr_signal(rval);
/* Or a simple select of a simple signal. */
} else if (expr_type == IVL_EX_SELECT) {
ivl_expr_t expr = ivl_expr_oper1(rval);
/* We must have a zero select base. */
if (ivl_expr_oper2(rval)) return ports;
/* We must be selecting a signal. */
if (ivl_expr_type(expr) != IVL_EX_SIGNAL) return ports;
rsig = ivl_expr_signal(expr);
} else return ports;
/* The R-value must have the same scope as the task. */
if (scope != ivl_signal_scope(rsig)) return ports;
/* It must not be an array element. */
if (ivl_signal_dimensions(rsig)) return ports;
/* It must be an output or inout port of the task. */
sig_name = ivl_signal_basename(rsig);
for (idx = 0; idx < ports; idx += 1) {
ivl_signal_t port = ivl_scope_port(scope, idx);
ivl_signal_port_t port_type = ivl_signal_port(port);
if ((port_type != IVL_SIP_OUTPUT) &&
(port_type != IVL_SIP_INOUT)) continue;
if (strcmp(sig_name, ivl_signal_basename(port)) == 0) break;
}
return idx;
}
/*
* Check to see if the bit based expression is of the form (expr) * <scale>
*/
static unsigned check_scaled_expr(ivl_expr_t expr, uint64_t scale,
const char *msg, unsigned must_match)
{
uint64_t scale_val;
int rtype;
if ((ivl_expr_type(expr) != IVL_EX_BINARY) ||
(ivl_expr_opcode(expr) != '*') ||
(ivl_expr_type(ivl_expr_oper2(expr)) != IVL_EX_NUMBER)) {
fprintf(stderr, "%s:%u: vlog95 error: %s expression/value "
"cannot be scaled.\n ",
ivl_expr_file(expr), ivl_expr_lineno(expr), msg);
vlog_errors += 1;
return 0;
}
scale_val = get_uint64_from_number(ivl_expr_oper2(expr), &rtype);
if (rtype > 0) {
fprintf(stderr, "%s:%u: vlog95 error: %s expression/value "
"scale coefficient was greater than 64 bits "
"(%d).\n", ivl_expr_file(expr),
ivl_expr_lineno(expr), msg, rtype);
vlog_errors += 1;
return 0;
}
if (rtype < 0) {
fprintf(stderr, "%s:%u: vlog95 error: %s expression/value "
"scale coefficient has an undefined bit.\n",
ivl_expr_file(expr), ivl_expr_lineno(expr), msg);
vlog_errors += 1;
return 0;
}
if (scale != scale_val) {
if (must_match) {
fprintf(stderr, "%s:%u: vlog95 error: %s expression/value "
"scale coefficient did not match expected "
"value (%"PRIu64" != %"PRIu64").\n",
ivl_expr_file(expr), ivl_expr_lineno(expr),
msg, scale, scale_val);
vlog_errors += 1;
return 0;
}
return 2;
}
/* Yes, this expression is of the correct form. */
return 1;
}
static void show_binary_expression(ivl_expr_t net, unsigned ind)
{
unsigned width = ivl_expr_width(net);
const char*sign = ivl_expr_signed(net)? "signed" : "unsigned";
const char*vt = vt_type_string(net);
ivl_expr_t oper1 = ivl_expr_oper1(net);
ivl_expr_t oper2 = ivl_expr_oper2(net);
fprintf(out, "%*s<\"%c\" width=%u, %s, type=%s>\n", ind, "",
ivl_expr_opcode(net), width, sign, vt);
if (oper1) {
show_expression(oper1, ind+3);
} else {
fprintf(out, "%*sERROR: Missing operand 1\n", ind+3, "");
stub_errors += 1;
}
if (oper2) {
show_expression(oper2, ind+3);
} else {
fprintf(out, "%*sERROR: Missing operand 2\n", ind+3, "");
stub_errors += 1;
}
switch (ivl_expr_opcode(net)) {
case '*':
if (ivl_expr_value(net) == IVL_VT_REAL) {
if (ivl_expr_width(net) != 1) {
fprintf(out, "%*sERROR: Result width incorrect. Expecting 1, got %u\n",
ind+3, "", ivl_expr_width(net));
stub_errors += 1;
}
} else {
/* The width of a multiply may be any width. The
implicit assumption is that the multiply
returns a width that is the sum of the widths
of the arguments, that is then truncated to the
desired width, never padded. The compiler will
automatically take care of sign extensions of
arguments, so that the code generator need only
generate an UNSIGNED multiply, and the result
will come out right. */
unsigned max_width = ivl_expr_width(oper1) + ivl_expr_width(oper2);
if (ivl_expr_width(net) > max_width) {
fprintf(out, "%*sERROR: Result width to width. Expecting <= %u, got %u\n",
ind+3, "", max_width, ivl_expr_width(net));
stub_errors += 1;
}
}
break;
default:
break;
}
}
static void emit_expr_ternary(ivl_scope_t scope, ivl_expr_t expr, unsigned wid)
{
fprintf(vlog_out, "(");
emit_expr(scope, ivl_expr_oper1(expr), 0);
fprintf(vlog_out, " ? ");
emit_expr(scope, ivl_expr_oper2(expr), wid);
fprintf(vlog_out, " : ");
emit_expr(scope, ivl_expr_oper3(expr), wid);
fprintf(vlog_out, ")");
}
static void draw_select_vec4(ivl_expr_t expr)
{
// This is the sub-expression to part-select.
ivl_expr_t subexpr = ivl_expr_oper1(expr);
// This is the base of the part select
ivl_expr_t base = ivl_expr_oper2(expr);
// This is the part select width
unsigned wid = ivl_expr_width(expr);
// Is the select base expression signed or unsigned?
char sign_suff = ivl_expr_signed(base)? 's' : 'u';
// Special Case: If the sub-expression is a STRING, then this
// is a select from that string.
if (ivl_expr_value(subexpr)==IVL_VT_STRING) {
assert(base);
assert(wid==8);
draw_eval_string(subexpr);
int base_idx = allocate_word();
draw_eval_expr_into_integer(base, base_idx);
fprintf(vvp_out, " %%substr/vec4 %d, %u;\n", base_idx, wid);
fprintf(vvp_out, " %%pop/str 1;\n");
clr_word(base_idx);
return;
}
if (ivl_expr_value(subexpr)==IVL_VT_DARRAY) {
ivl_signal_t sig = ivl_expr_signal(subexpr);
assert(sig);
assert( (ivl_signal_data_type(sig)==IVL_VT_DARRAY)
|| (ivl_signal_data_type(sig)==IVL_VT_QUEUE) );
assert(base);
draw_eval_expr_into_integer(base, 3);
fprintf(vvp_out, " %%load/dar/vec4 v%p_0;\n", sig);
return;
}
if (test_immediate_vec4_ok(base)) {
unsigned long val0, valx;
unsigned base_wid;
make_immediate_vec4_words(base, &val0, &valx, &base_wid);
assert(valx == 0);
draw_eval_vec4(subexpr);
fprintf(vvp_out, " %%parti/%c %u, %lu, %u;\n",
sign_suff, wid, val0, base_wid);
} else {
draw_eval_vec4(subexpr);
draw_eval_vec4(base);
fprintf(vvp_out, " %%part/%c %u;\n", sign_suff, wid);
}
}
static void show_new_expression(ivl_expr_t net, unsigned ind)
{
switch (ivl_expr_value(net)) {
case IVL_VT_CLASS:
fprintf(out, "%*snew <class_type>\n", ind, "");
if (ivl_expr_oper1(net)) {
fprintf(out, "%*sERROR: class_new expression has a size!\n",
ind+3, "");
show_expression(ivl_expr_oper1(net), ind+3);
stub_errors += 1;
}
if (ivl_expr_oper2(net)){
fprintf(out, "%*sERROR: class_new with array element initializer!\n",
ind+3, "");
show_expression(ivl_expr_oper2(net), ind+3);
stub_errors += 1;
}
break;
case IVL_VT_DARRAY:
fprintf(out, "%*snew [] <type>\n", ind, "");
if (ivl_expr_oper1(net)) {
show_expression(ivl_expr_oper1(net), ind+3);
} else {
fprintf(out, "%*sERROR: darray_new missing size expression\n",
ind+3, "");
stub_errors += 1;
}
/* The IVL_EX_NEW expression may include an element
initializer. This may be an array pattern or simple
expression. */
if (ivl_expr_oper2(net)) {
show_expression(ivl_expr_oper2(net), ind+3);
}
break;
default:
fprintf(out, "%*snew ERROR: expression type: %s\n",
ind+3, "", vt_type_string(net));
stub_errors += 1;
break;
}
}
static void emit_expr_select(ivl_scope_t scope, ivl_expr_t expr, unsigned wid)
{
ivl_expr_t sel_expr = ivl_expr_oper2(expr);
ivl_expr_t sig_expr = ivl_expr_oper1(expr);
ivl_select_type_t sel_type = ivl_expr_sel_type(expr);
if (sel_expr) {
unsigned width = ivl_expr_width(expr);
ivl_expr_type_t type = ivl_expr_type(sig_expr);
assert(width > 0);
/* The compiler uses selects for some shifts. */
if (type != IVL_EX_NUMBER && type != IVL_EX_SIGNAL) {
fprintf(vlog_out, "(" );
emit_select_name(scope, sig_expr, wid);
fprintf(vlog_out, " >> " );
emit_scaled_expr(scope, sel_expr, 1, 0);
fprintf(vlog_out, ")" );
} else {
/* A constant/parameter must be zero based in 1364-1995
* so keep the compiler generated normalization. This
* does not always work for selects before the parameter
* since 1364-1995 does not support signed math. */
int msb = 1;
int lsb = 0;
if (type == IVL_EX_SIGNAL) {
ivl_signal_t sig = ivl_expr_signal(sig_expr);
msb = ivl_signal_msb(sig);
lsb = ivl_signal_lsb(sig);
}
/* A bit select. */
if (width == 1) {
emit_select_name(scope, sig_expr, wid);
fprintf(vlog_out, "[");
emit_scaled_expr(scope, sel_expr, msb, lsb);
fprintf(vlog_out, "]");
} else {
if (ivl_expr_type(sel_expr) == IVL_EX_NUMBER) {
/* A constant part select. */
emit_select_name(scope, sig_expr, wid);
emit_scaled_range(scope, sel_expr, width,
msb, lsb);
} else {
/* An indexed part select. */
assert(sel_type != IVL_SEL_OTHER);
emit_expr_ips(scope, sig_expr, sel_expr,
sel_type, width, msb, lsb);
}
}
}
} else {
// HERE: Should this sign extend if the expression is signed?
emit_expr(scope, sig_expr, wid);
}
}
static void string_ex_select(ivl_expr_t expr)
{
/* The sube references the expression to be selected from. */
ivl_expr_t sube = ivl_expr_oper1(expr);
/* This is the select expression */
ivl_expr_t shift= ivl_expr_oper2(expr);
/* Assume the sub-expression is a signal */
ivl_signal_t sig = ivl_expr_signal(sube);
assert(ivl_signal_data_type(sig) == IVL_VT_DARRAY);
draw_eval_expr_into_integer(shift, 3);
fprintf(vvp_out, " %%load/dar/str v%p_0;\n", sig);
}
static void show_ternary_expression(ivl_expr_t net, unsigned ind)
{
unsigned width = ivl_expr_width(net);
const char*sign = ivl_expr_signed(net)? "signed" : "unsigned";
const char*vt = vt_type_string(net);
fprintf(out, "%*s<ternary width=%u, %s type=%s>\n", ind, "",
width, sign, vt);
show_expression(ivl_expr_oper1(net), ind+4);
show_expression(ivl_expr_oper2(net), ind+4);
show_expression(ivl_expr_oper3(net), ind+4);
if (ivl_expr_width(ivl_expr_oper2(net)) != width) {
fprintf(out, "ERROR: Width of TRUE expressions is %u, not %u\n",
ivl_expr_width(ivl_expr_oper2(net)), width);
stub_errors += 1;
}
if (ivl_expr_width(ivl_expr_oper3(net)) != width) {
fprintf(out, "ERROR: Width of FALSE expressions is %u, not %u\n",
ivl_expr_width(ivl_expr_oper3(net)), width);
stub_errors += 1;
}
}
static int eval_object_shallowcopy(ivl_expr_t ex)
{
ivl_expr_t dest = ivl_expr_oper1(ex);
ivl_expr_t src = ivl_expr_oper2(ex);
draw_eval_object(dest);
draw_eval_object(src);
/* The %scopy opcode pops the top of the object stack as the
source object, and shallow-copies it to the new top, the
destination object. The destination is left on the top of
the stack. */
fprintf(vvp_out, " %%scopy;\n");
return 0;
}
static void draw_ternary_vec4(ivl_expr_t expr)
{
ivl_expr_t cond = ivl_expr_oper1(expr);
ivl_expr_t true_ex = ivl_expr_oper2(expr);
ivl_expr_t false_ex = ivl_expr_oper3(expr);
unsigned lab_true = local_count++;
unsigned lab_out = local_count++;
int use_flag = draw_eval_condition(cond);
/* The condition flag is used after possibly other statements,
so we need to put it into a non-common place. Allocate a
safe flag bit and move the condition to the flag position. */
if (use_flag < 8) {
int tmp_flag = allocate_flag();
assert(tmp_flag >= 8);
fprintf(vvp_out, " %%flag_mov %d, %d;\n", tmp_flag, use_flag);
use_flag = tmp_flag;
}
fprintf(vvp_out, " %%jmp/0 T_%u.%u, %d;\n", thread_count, lab_true, use_flag);
/* If the condition is true or xz (not false), we need the true
expression. If the condition is true, then we ONLY need the
true expression. */
draw_eval_vec4(true_ex);
fprintf(vvp_out, " %%jmp/1 T_%u.%u, %d;\n", thread_count, lab_out, use_flag);
fprintf(vvp_out, "T_%u.%u ; End of true expr.\n", thread_count, lab_true);
/* If the condition is false or xz (not true), we need the false
expression. If the condition is false, then we ONLY need
the false expression. */
draw_eval_vec4(false_ex);
fprintf(vvp_out, " %%jmp/0 T_%u.%u, %d;\n", thread_count, lab_out, use_flag);
fprintf(vvp_out, " ; End of false expr.\n");
/* Here, the condition is not true or false, it is xz. Both
the true and false expressions have been pushed onto the
stack, we just need to blend the bits. */
fprintf(vvp_out, " %%blend;\n");
fprintf(vvp_out, "T_%u.%u;\n", thread_count, lab_out);
clr_flag(use_flag);
}
static int draw_binary_real(ivl_expr_t exp)
{
int l, r = -1;
l = draw_eval_real(ivl_expr_oper1(exp));
r = draw_eval_real(ivl_expr_oper2(exp));
switch (ivl_expr_opcode(exp)) {
case '+':
fprintf(vvp_out, " %%add/wr %d, %d;\n", l, r);
break;
case '-':
fprintf(vvp_out, " %%sub/wr %d, %d;\n", l, r);
break;
case '*':
fprintf(vvp_out, " %%mul/wr %d, %d;\n", l, r);
break;
case '/':
fprintf(vvp_out, " %%div/wr %d, %d;\n", l, r);
break;
case '%':
{ struct vector_info res = draw_eval_expr(exp, STUFF_OK_XZ);
l = allocate_word();
fprintf(vvp_out, " %%ix/get %d, %u, %u;\n",
l, res.base, res.wid);
fprintf(vvp_out, " %%cvt/ri %d, %d;\n", l, l);
clr_vector(res);
}
break;
default:
fprintf(stderr, "XXXX draw_binary_real(%c)\n",
ivl_expr_opcode(exp));
assert(0);
}
if (r >= 0) clr_word(r);
return l;
}
static void show_select_expression(ivl_expr_t net, unsigned ind)
{
unsigned width = ivl_expr_width(net);
const char*sign = ivl_expr_signed(net)? "signed" : "unsigned";
const char*vt = vt_type_string(net);
ivl_expr_t oper1 = ivl_expr_oper1(net);
ivl_expr_t oper2 = ivl_expr_oper2(net);
if (ivl_expr_value(oper1) == IVL_VT_STRING) {
/* If the sub-expression is a STRING, then this is a
substring and the code generator will handle it
differently. */
fprintf(out, "%*s<substring: width=%u bits, %u bytes>\n", ind, "", width, width/8);
if (width%8 != 0) {
fprintf(out, "%*sERROR: Width should be a multiple of 8 bits.\n", ind, "");
stub_errors += 1;
}
assert(oper1);
show_expression(oper1, ind+3);
if (oper2) {
show_expression(oper2, ind+3);
} else {
fprintf(out, "%*sERROR: oper2 missing! Pad makes no sense for IVL_VT_STRING expressions.\n", ind+3, "");
stub_errors += 1;
}
} else if (oper2) {
/* If oper2 is present, then it is the base of a part
select. The width of the expression defines the range
of the part select. */
fprintf(out, "%*s<select: width=%u, %s, type=%s>\n", ind, "",
width, sign, vt);
show_expression(oper1, ind+3);
show_expression(oper2, ind+3);
} else {
/* There is no base expression so this is a pad
operation. The sub-expression is padded (signed or
unsigned as appropriate) to the expression width. */
fprintf(out, "%*s<expr pad: width=%u, %s>\n", ind, "",
width, sign);
show_expression(oper1, ind+3);
}
}
static void show_shallowcopy(ivl_expr_t net, unsigned ind)
{
ivl_expr_t oper1 = ivl_expr_oper1(net);
ivl_expr_t oper2 = ivl_expr_oper2(net);
fprintf(out, "%*s<shallow_copy>\n", ind, "");
show_expression(oper1, ind+3);
show_expression(oper2, ind+3);
if (ivl_expr_value(oper1) != ivl_expr_value(oper2)) {
fprintf(out, "%*sERROR: Shallow copy operand types must match.\n", ind+3,"");
stub_errors += 1;
}
if (ivl_expr_value(oper1)!=IVL_VT_CLASS && ivl_expr_value(oper1)!=IVL_VT_DARRAY) {
fprintf(out, "%*sERROR: Operand 1 type is %s\n", ind+3, "", vt_type_string(oper1));
stub_errors += 1;
}
}
static void draw_binary_vec4_compare_string(ivl_expr_t expr)
{
draw_eval_string(ivl_expr_oper1(expr));
draw_eval_string(ivl_expr_oper2(expr));
switch (ivl_expr_opcode(expr)) {
case 'e': /* == */
fprintf(vvp_out, " %%cmp/str;\n");
fprintf(vvp_out, " %%flag_get/vec4 4;\n");
break;
case 'n': /* != */
fprintf(vvp_out, " %%cmp/str;\n");
fprintf(vvp_out, " %%flag_inv 4;\n");
fprintf(vvp_out, " %%flag_get/vec4 4;\n");
break;
default:
assert(0);
}
}
/*
* Icarus translated wait(<expr) <stmt> into
* begin
* while (<expr> !== 1'b1) @(<expr sensitivities>);
* <stmt>
* end
* This routine looks for this pattern and turns it back into a
* wait statement.
*/
static unsigned is_wait(ivl_scope_t scope, ivl_statement_t stmt)
{
ivl_statement_t while_wait, wait, wait_stmt;
ivl_expr_t while_expr, expr;
const char *bits;
/* We must have two block elements. */
if (ivl_stmt_block_count(stmt) != 2) return 0;
/* The first must be a while. */
while_wait = ivl_stmt_block_stmt(stmt, 0);
if (ivl_statement_type(while_wait) != IVL_ST_WHILE) return 0;
/* That has a wait with a NOOP statement. */
wait = ivl_stmt_sub_stmt(while_wait);
if (ivl_statement_type(wait) != IVL_ST_WAIT) return 0;
wait_stmt = ivl_stmt_sub_stmt(wait);
if (ivl_statement_type(wait_stmt) != IVL_ST_NOOP) return 0;
/* Check that the while condition has the correct form. */
while_expr = ivl_stmt_cond_expr(while_wait);
if (ivl_expr_type(while_expr) != IVL_EX_BINARY) return 0;
if (ivl_expr_opcode(while_expr) != 'N') return 0;
/* Has a second operator that is a constant 1'b1. */
expr = ivl_expr_oper2(while_expr);
if (ivl_expr_type(expr) != IVL_EX_NUMBER) return 0;
if (ivl_expr_width(expr) != 1) return 0;
bits = ivl_expr_bits(expr);
if (*bits != '1') return 0;
// HERE: There is no easy way to verify that the @ sensitivity list
// matches the first expression so we don't check for that yet.
/* And finally the two statements that represent the wait must
* have the same line number as the block. */
if ((ivl_stmt_lineno(stmt) != ivl_stmt_lineno(while_wait)) ||
(ivl_stmt_lineno(stmt) != ivl_stmt_lineno(wait))) {
return 0;
}
/* The pattern matched so generate the appropriate code. */
fprintf(vlog_out, "%*cwait(", get_indent(), ' ');
emit_expr(scope, ivl_expr_oper1(while_expr), 0);
fprintf(vlog_out, ")");
emit_stmt_file_line(stmt);
single_indent = 1;
emit_stmt(scope, ivl_stmt_block_stmt(stmt, 1));
return 1;
}
static void draw_binary_vec4_le_string(ivl_expr_t expr)
{
ivl_expr_t le = ivl_expr_oper1(expr);
ivl_expr_t re = ivl_expr_oper2(expr);
switch (ivl_expr_opcode(expr)) {
case '<':
draw_eval_string(le);
draw_eval_string(re);
fprintf(vvp_out, " %%cmp/str;\n");
fprintf(vvp_out, " %%flag_get/vec4 5;\n");
break;
case 'L': /* <= */
draw_eval_string(le);
draw_eval_string(re);
fprintf(vvp_out, " %%cmp/str;\n");
fprintf(vvp_out, " %%flag_get/vec4 4;\n");
fprintf(vvp_out, " %%flag_get/vec4 5;\n");
fprintf(vvp_out, " %%or;\n");
break;
case '>':
draw_eval_string(re);
draw_eval_string(le);
fprintf(vvp_out, " %%cmp/str;\n");
fprintf(vvp_out, " %%flag_get/vec4 5;\n");
break;
case 'G': /* >= */
draw_eval_string(re);
draw_eval_string(le);
fprintf(vvp_out, " %%cmp/str;\n");
fprintf(vvp_out, " %%flag_get/vec4 4;\n");
fprintf(vvp_out, " %%flag_get/vec4 5;\n");
fprintf(vvp_out, " %%or;\n");
break;
default:
assert(0);
break;
}
}
static int draw_condition_binary_lor(ivl_expr_t expr)
{
ivl_expr_t le = ivl_expr_oper1(expr);
ivl_expr_t re = ivl_expr_oper2(expr);
int lx = draw_eval_condition(le);
if (lx < 8) {
int tmp = allocate_flag();
fprintf(vvp_out, " %%flag_mov %d, %d;\n", tmp, lx);
lx = tmp;
}
int rx = draw_eval_condition(re);
fprintf(vvp_out, " %%flag_or %d, %d;\n", rx, lx);
clr_flag(lx);
return rx;
}
static int draw_condition_binary_real_le(ivl_expr_t expr)
{
ivl_expr_t le = ivl_expr_oper1(expr);
ivl_expr_t re = ivl_expr_oper2(expr);
ivl_expr_t tmp;
char use_opcode = ivl_expr_opcode(expr);
/* If this is a > or >=, then convert it to < or <= by
swapping the operands. Adjust the opcode to match. */
switch (use_opcode) {
case 'G':
tmp = le;
le = re;
re = tmp;
use_opcode = 'L';
break;
case '>':
tmp = le;
le = re;
re = tmp;
use_opcode = '<';
break;
}
draw_eval_real(le);
draw_eval_real(re);
fprintf(vvp_out, " %%cmp/wr;\n");
switch (use_opcode) {
case '<':
return 5;
case 'L':
fprintf(vvp_out, " %%flag_or 5, 4;\n");
return 5;
default:
assert(0);
return -1;
}
}
/*
* We can convert any 2^n ** <unsigned variable> expression to
* 1 << (n * <unsigned variable>). If the variable is signed then we need
* to add a check for less than zero and for that case return 0.
*/
static unsigned emit_power_as_shift(ivl_scope_t scope, ivl_expr_t expr,
unsigned wid)
{
int rtype;
int64_t value, scale;
unsigned is_signed_rval = 0;
unsigned expr_wid;
ivl_expr_t lval = ivl_expr_oper1(expr);
ivl_expr_t rval = ivl_expr_oper2(expr);
/* The L-value must be a number. */
if (ivl_expr_type(lval) != IVL_EX_NUMBER) return 0;
/* The L-value must of the form 2^n. */
value = get_int64_from_number(lval, &rtype);
if (rtype) return 0;
expr_wid = ivl_expr_width(lval);
if (value < 2) return 0;
if (value % 2) return 0;
/* Generate the appropriate conversion. */
if (ivl_expr_signed(rval)) {
emit_expr(scope, rval, 0);
fprintf(vlog_out, " < 0 ? %u'h0 : (", expr_wid);
is_signed_rval = 1;
}
scale = value / 2;
fprintf(vlog_out, "%u'h1 << ", expr_wid);
if (scale != 1) {
if (is_signed_rval) {
fprintf(vlog_out, "(%"PRId64, scale);
} else {
fprintf(vlog_out, "(%u'h%"PRIx64,
ivl_expr_width(rval), scale);
}
fprintf(vlog_out, " * ");
}
emit_expr(scope, rval, 0);
if (scale != 1) fprintf(vlog_out, ")");
if (is_signed_rval) fprintf(vlog_out, ")");
return 1;
}
static void draw_binary_vec4_lor(ivl_expr_t expr)
{
ivl_expr_t le = ivl_expr_oper1(expr);
ivl_expr_t re = ivl_expr_oper2(expr);
/* Push the left expression. Reduce it to a single bit if
necessary. */
draw_eval_vec4(le);
if (ivl_expr_width(le) > 1)
fprintf(vvp_out, " %%or/r;\n");
/* Now push the right expression. Again, reduce to a single
bit if necessary. */
draw_eval_vec4(re);
if (ivl_expr_width(re) > 1)
fprintf(vvp_out, " %%or/r;\n");
fprintf(vvp_out, " %%or;\n");
if (ivl_expr_width(expr) > 1)
fprintf(vvp_out, " %%pad/u %u;\n", ivl_expr_width(expr));
}
static void draw_binary_vec4_le(ivl_expr_t expr)
{
ivl_expr_t le = ivl_expr_oper1(expr);
ivl_expr_t re = ivl_expr_oper2(expr);
ivl_expr_t tmp;
if ((ivl_expr_value(le) == IVL_VT_REAL)
|| (ivl_expr_value(re) == IVL_VT_REAL)) {
draw_binary_vec4_le_real(expr);
return;
}
char use_opcode = ivl_expr_opcode(expr);
char s_flag = (ivl_expr_signed(le) && ivl_expr_signed(re)) ? 's' : 'u';
/* If this is a > or >=, then convert it to < or <= by
swapping the operands. Adjust the opcode to match. */
switch (use_opcode) {
case 'G':
tmp = le;
le = re;
re = tmp;
use_opcode = 'L';
break;
case '>':
tmp = le;
le = re;
re = tmp;
use_opcode = '<';
break;
}
if ((ivl_expr_value(le)==IVL_VT_STRING)
&& (ivl_expr_value(re)==IVL_VT_STRING)) {
draw_binary_vec4_le_string(expr);
return;
}
if ((ivl_expr_value(le)==IVL_VT_STRING)
&& (ivl_expr_type(re)==IVL_EX_STRING)) {
draw_binary_vec4_le_string(expr);
return;
}
if ((ivl_expr_type(le)==IVL_EX_STRING)
&& (ivl_expr_value(re)==IVL_VT_STRING)) {
draw_binary_vec4_le_string(expr);
return;
}
/* NOTE: I think I would rather the elaborator handle the
operand widths. When that happens, take this code out. */
unsigned use_wid = ivl_expr_width(le);
if (ivl_expr_width(re) > use_wid)
use_wid = ivl_expr_width(re);
draw_eval_vec4(le);
resize_vec4_wid(le, use_wid);
if (ivl_expr_width(re)==use_wid && test_immediate_vec4_ok(re)) {
/* Special case: If the right operand can be handled as
an immediate operand, then use that instead. */
char opcode[8];
snprintf(opcode, sizeof opcode, "%%cmpi/%c", s_flag);
draw_immediate_vec4(re, opcode);
} else {
draw_eval_vec4(re);
resize_vec4_wid(re, use_wid);
fprintf(vvp_out, " %%cmp/%c;\n", s_flag);
}
switch (use_opcode) {
case 'L':
fprintf(vvp_out, " %%flag_get/vec4 4;\n");
fprintf(vvp_out, " %%flag_get/vec4 5;\n");
fprintf(vvp_out, " %%or;\n");
break;
case '<':
fprintf(vvp_out, " %%flag_get/vec4 5;\n");
break;
default:
assert(0);
break;
}
}
static int get_vpi_taskfunc_signal_arg(struct args_info *result,
ivl_expr_t expr)
{
char buffer[4096];
switch (ivl_expr_type(expr)) {
case IVL_EX_SIGNAL:
/* If the signal node is narrower than the signal itself,
then this is a part select so I'm going to need to
evaluate the expression.
Also, if the signedness of the expression is different
from the signedness of the signal. This could be
caused by a $signed or $unsigned system function.
If I don't need to do any evaluating, then skip it as
I'll be passing the handle to the signal itself. */
if (ivl_expr_width(expr) !=
ivl_signal_width(ivl_expr_signal(expr))) {
/* This should never happen since we have IVL_EX_SELECT. */
return 0;
} else if (ivl_expr_signed(expr) !=
ivl_signal_signed(ivl_expr_signal(expr))) {
return 0;
} else if (is_fixed_memory_word(expr)) {
/* This is a word of a non-array, or a word of a net
array, so we can address the word directly. */
ivl_signal_t sig = ivl_expr_signal(expr);
unsigned use_word = 0;
ivl_expr_t word_ex = ivl_expr_oper1(expr);
if (word_ex) {
/* Some array select have been evaluated. */
if (number_is_immediate(word_ex,IMM_WID, 0)) {
assert(! number_is_unknown(word_ex));
use_word = get_number_immediate(word_ex);
word_ex = 0;
}
}
if (word_ex) return 0;
assert(word_ex == 0);
snprintf(buffer, sizeof buffer, "v%p_%u", sig, use_word);
result->text = strdup(buffer);
return 1;
} else {
/* What's left, this is the work of a var array.
Create the right code to handle it. */
ivl_signal_t sig = ivl_expr_signal(expr);
unsigned use_word = 0;
unsigned use_word_defined = 0;
ivl_expr_t word_ex = ivl_expr_oper1(expr);
if (word_ex) {
/* Some array select have been evaluated. */
if (number_is_immediate(word_ex, IMM_WID, 0)) {
assert(! number_is_unknown(word_ex));
use_word = get_number_immediate(word_ex);
use_word_defined = 1;
word_ex = 0;
}
}
if (word_ex && (ivl_expr_type(word_ex)==IVL_EX_SIGNAL ||
ivl_expr_type(word_ex)==IVL_EX_SELECT)) {
/* Special case: the index is a signal/select. */
result->child = calloc(1, sizeof(struct args_info));
if (get_vpi_taskfunc_signal_arg(result->child,
word_ex)) {
snprintf(buffer, sizeof buffer, "&A<v%p, %s >",
sig, result->child->text);
free(result->child->text);
} else {
free(result->child);
result->child = NULL;
return 0;
}
} else if (word_ex) {
/* Fallback case: evaluate expression. */
struct vector_info av;
av = draw_eval_expr(word_ex, STUFF_OK_XZ);
snprintf(buffer, sizeof buffer, "&A<v%p, %u %u \"%s\">",
sig, av.base, av.wid,
(ivl_expr_signed(word_ex) ? "s" : "u"));
result->vec = av;
result->vec_flag = 1;
} else {
assert(use_word_defined);
snprintf(buffer, sizeof buffer, "&A<v%p, %u>",
sig, use_word);
}
result->text = strdup(buffer);
return 1;
}
case IVL_EX_SELECT: {
ivl_expr_t vexpr = ivl_expr_oper1(expr);
ivl_expr_t bexpr;
ivl_expr_t wexpr;
assert(vexpr);
/* This code is only for signals or selects. */
if (ivl_expr_type(vexpr) != IVL_EX_SIGNAL &&
ivl_expr_type(vexpr) != IVL_EX_SELECT) return 0;
/* The signal is part of an array. */
/* Add &APV<> code here when it is finished. */
bexpr = ivl_expr_oper2(expr);
/* This is a pad operation. */
if (!bexpr) return 0;
wexpr = ivl_expr_oper1(vexpr);
/* If vexpr has an operand, then that operand is a word
index and we are taking a select from an array
word. This would come up in expressions like
"array[<word>][<part>]" where wexpr is <word> */
if (wexpr && number_is_immediate(wexpr, 64, 1)
&& number_is_immediate(bexpr, 64, 1)) {
assert(! number_is_unknown(bexpr));
assert(! number_is_unknown(wexpr));
snprintf(buffer, sizeof buffer, "&APV<v%p, %ld, %ld, %u>",
ivl_expr_signal(vexpr),
get_number_immediate(wexpr),
get_number_immediate(bexpr),
ivl_expr_width(expr));
} else if (wexpr) {
return 0;
/* This is a constant bit/part select. */
} else if (number_is_immediate(bexpr, 64, 1)) {
assert(! number_is_unknown(bexpr));
snprintf(buffer, sizeof buffer, "&PV<v%p_0, %ld, %u>",
ivl_expr_signal(vexpr),
get_number_immediate(bexpr),
ivl_expr_width(expr));
/* This is an indexed bit/part select. */
} else if (ivl_expr_type(bexpr) == IVL_EX_SIGNAL ||
ivl_expr_type(bexpr) == IVL_EX_SELECT) {
/* Special case: the base is a signal/select. */
result->child = calloc(1, sizeof(struct args_info));
if (get_vpi_taskfunc_signal_arg(result->child, bexpr)) {
snprintf(buffer, sizeof buffer, "&PV<v%p_0, %s, %u>",
ivl_expr_signal(vexpr),
result->child->text,
ivl_expr_width(expr));
free(result->child->text);
} else {
free(result->child);
result->child = NULL;
return 0;
}
} else {
/* Fallback case: evaluate the expression. */
struct vector_info rv;
rv = draw_eval_expr(bexpr, STUFF_OK_XZ);
snprintf(buffer, sizeof buffer,
"&PV<v%p_0, %u %u \"%s\", %u>",
ivl_expr_signal(vexpr),
rv.base, rv.wid,
(ivl_expr_signed(bexpr) ? "s" : "u"),
ivl_expr_width(expr));
result->vec = rv;
result->vec_flag = 1;
}
result->text = strdup(buffer);
return 1;
}
default:
return 0;
}
}
static void draw_binary_vec4_compare_class(ivl_expr_t expr)
{
ivl_expr_t le = ivl_expr_oper1(expr);
ivl_expr_t re = ivl_expr_oper2(expr);
if (ivl_expr_type(le) == IVL_EX_NULL) {
ivl_expr_t tmp = le;
le = re;
re = tmp;
}
/* Special case: If both operands are null, then the
expression has a constant value. */
if (ivl_expr_type(le)==IVL_EX_NULL && ivl_expr_type(re)==IVL_EX_NULL) {
switch (ivl_expr_opcode(expr)) {
case 'e': /* == */
fprintf(vvp_out, " %%pushi/vec4 1, 0, 1;\n");
break;
case 'n': /* != */
fprintf(vvp_out, " %%pushi/vec4 0, 0, 1;\n");
break;
default:
assert(0);
break;
}
return;
}
/* A signal/variable is compared to null. Implement this with
the %test_nul statement, which peeks at the variable
contents directly. */
if (ivl_expr_type(re)==IVL_EX_NULL && ivl_expr_type(le)==IVL_EX_SIGNAL) {
ivl_signal_t sig= ivl_expr_signal(le);
if (ivl_signal_dimensions(sig) == 0) {
fprintf(vvp_out, " %%test_nul v%p_0;\n", sig);
} else {
ivl_expr_t word_ex = ivl_expr_oper1(le);
int word_ix = allocate_word();
draw_eval_expr_into_integer(word_ex, word_ix);
fprintf(vvp_out, " %%test_nul/a v%p, %d;\n", sig, word_ix);
clr_word(word_ix);
}
if (ivl_expr_opcode(expr) == 'n')
fprintf(vvp_out, " %%flag_inv 4;\n");
fprintf(vvp_out, " %%flag_get/vec4 4;\n");
return;
}
if (ivl_expr_type(re)==IVL_EX_NULL && ivl_expr_type(le)==IVL_EX_PROPERTY) {
ivl_signal_t sig = ivl_expr_signal(le);
unsigned pidx = ivl_expr_property_idx(le);
ivl_expr_t idx_expr = ivl_expr_oper1(le);
int idx = 0;
/* If the property has an array index, then evaluate it
into an index register. */
if ( idx_expr ) {
idx = allocate_word();
draw_eval_expr_into_integer(idx_expr, idx);
}
fprintf(vvp_out, " %%load/obj v%p_0;\n", sig);
fprintf(vvp_out, " %%test_nul/prop %u, %d;\n", pidx, idx);
fprintf(vvp_out, " %%pop/obj 1, 0;\n");
if (ivl_expr_opcode(expr) == 'n')
fprintf(vvp_out, " %%flag_inv 4;\n");
fprintf(vvp_out, " %%flag_get/vec4 4;\n");
if (idx != 0) clr_word(idx);
return;
}
fprintf(stderr, "SORRY: Compare class handles not implemented\n");
fprintf(vvp_out, " ; XXXX compare class handles. re-type=%d, le-type=%d\n",
ivl_expr_type(re), ivl_expr_type(le));
vvp_errors += 1;
}
static void draw_binary_vec4_compare(ivl_expr_t expr)
{
ivl_expr_t le = ivl_expr_oper1(expr);
ivl_expr_t re = ivl_expr_oper2(expr);
if ((ivl_expr_value(le) == IVL_VT_REAL)
|| (ivl_expr_value(re) == IVL_VT_REAL)) {
draw_binary_vec4_compare_real(expr);
return;
}
if ((ivl_expr_value(le)==IVL_VT_STRING)
&& (ivl_expr_value(re)==IVL_VT_STRING)) {
draw_binary_vec4_compare_string(expr);
return;
}
if ((ivl_expr_value(le)==IVL_VT_STRING)
&& (ivl_expr_type(re)==IVL_EX_STRING)) {
draw_binary_vec4_compare_string(expr);
return;
}
if ((ivl_expr_type(le)==IVL_EX_STRING)
&& (ivl_expr_value(re)==IVL_VT_STRING)) {
draw_binary_vec4_compare_string(expr);
return;
}
if ((ivl_expr_value(le)==IVL_VT_CLASS)
&& (ivl_expr_value(re)==IVL_VT_CLASS)) {
draw_binary_vec4_compare_class(expr);
return;
}
unsigned use_wid = ivl_expr_width(le);
if (ivl_expr_width(re) > use_wid)
use_wid = ivl_expr_width(re);
draw_eval_vec4(le);
resize_vec4_wid(le, use_wid);
draw_eval_vec4(re);
resize_vec4_wid(re, use_wid);
switch (ivl_expr_opcode(expr)) {
case 'e': /* == */
fprintf(vvp_out, " %%cmp/e;\n");
fprintf(vvp_out, " %%flag_get/vec4 4;\n");
break;
case 'n': /* != */
fprintf(vvp_out, " %%cmp/e;\n");
fprintf(vvp_out, " %%flag_inv 4;\n");
fprintf(vvp_out, " %%flag_get/vec4 4;\n");
break;
case 'E': /* === */
fprintf(vvp_out, " %%cmp/e;\n");
fprintf(vvp_out, " %%flag_get/vec4 6;\n");
break;
case 'N': /* !== */
fprintf(vvp_out, " %%cmp/e;\n");
fprintf(vvp_out, " %%flag_inv 6;\n");
fprintf(vvp_out, " %%flag_get/vec4 6;\n");
break;
default:
assert(0);
}
}