/* ----------------------------------------------------
* deregister the scheduler
*/
PUBLIC IX_STATUS
ixAtmdAccPortTxScheduledModeDisable (IxAtmLogicalPort port)
{
IX_STATUS returnStatus = IX_SUCCESS;
/* check parameters */
if ((IX_UTOPIA_MAX_PORTS <= port) ||
(IX_UTOPIA_PORT_0 > port) ||
(!ixAtmdAccPortConfigured (port)))
{
returnStatus = IX_FAIL;
} /* end of if(port) */
if (ixAtmdAccTxCfgInitDone)
{
IX_ATMDACC_TX_LOCK_GET ();
/* check no channel is already set on this port */
if (!ixAtmdAccTxCfgPortVcsExist (port))
{
ixAtmdAccTxCfgSchCallbackUnregister (port);
returnStatus = IX_SUCCESS;
} /* end of if(ixAtmdAccTxCfgPortVcsExist) */
IX_ATMDACC_TX_LOCK_RELEASE ();
}
return returnStatus;
}
/* ------------------------------------------------
* set the tx queue nearly-empty threshold
*/
PUBLIC IX_STATUS
ixAtmdAccPortTxCallbackRegister (IxAtmLogicalPort port,
unsigned int numberOfCells,
IxAtmdAccPortTxLowCallback callback)
{
IX_STATUS returnStatus = IX_FAIL;
if (ixAtmdAccTxCfgInitDone &&
(port >= IX_UTOPIA_PORT_0) &&
(port < IX_UTOPIA_MAX_PORTS) &&
(callback != NULL))
{
IX_ATMDACC_TX_LOCK_GET ();
if(ixAtmdAccPortConfigured (port) &&
!ixAtmdAccTxCfgPortVcsExist (port))
{
returnStatus = ixAtmdAccTxCfgTxCallbackRegister (port, numberOfCells, callback);
}
IX_ATMDACC_TX_LOCK_RELEASE ();
} /* end of if(ixAtmdAccTxCfgInitDone) */
return returnStatus;
}
/* -----------------------------------------
* Functions visable in this file only
* ----------------------------------------- */
PRIVATE IX_STATUS
ixAtmdAccPortStateChange (IxAtmLogicalPort port, IxAtmdAccPortState newState)
{
IX_STATUS returnStatus = IX_SUCCESS;
/* Check parameters */
if ((port < IX_UTOPIA_PORT_0)
||(port >= IX_UTOPIA_MAX_PORTS)
|| !ixAtmdAccPortConfigured(port))
{
returnStatus = IX_FAIL;
}
if (returnStatus == IX_SUCCESS)
{
IX_ATMDACC_PORTMGMT_LOCK_GET();
/* Notify the interested party */
returnStatus = stateChangeRequest(port, newState);
/* update Stats */
portRequestStats[port]++;
IX_ATMDACC_PORTMGMT_LOCK_RELEASE ();
} /* end of if(returnStatus) */
return returnStatus;
}
/* ----------------------------------------------
*/
PRIVATE IX_STATUS
ixAtmdAccPortStateQuery (IxAtmLogicalPort port,
IxAtmdAccPortState state,
BOOL *paramError)
{
IX_STATUS returnStatus = IX_SUCCESS;
*paramError = FALSE;
/* Check parameters */
if ((port < IX_UTOPIA_PORT_0)
||(port >= IX_UTOPIA_MAX_PORTS)
|| !ixAtmdAccPortConfigured(port))
{
*paramError = TRUE;
returnStatus = IX_SUCCESS;
}
else if ((state != IX_ATMD_PORT_ENABLED) &&
(state != IX_ATMD_PORT_DISABLED))
{
*paramError = TRUE;
returnStatus = IX_FAIL;
}
else if (returnStatus == IX_SUCCESS)
{
IX_ATMDACC_PORTMGMT_LOCK_GET();
if (state == IX_ATMD_PORT_ENABLED)
{
if (!isEnabledQuery (port))
{
returnStatus = IX_FAIL;
}
}
else
{
if (!isDisableComplete (port))
{
returnStatus = IX_FAIL;
}
} /* end of if-else(state) */
IX_ATMDACC_PORTMGMT_LOCK_RELEASE();
} /* end of if(returnStatus) */
return returnStatus;
}
/* ----------------------------------------------------
* check the input params for ixAtmdAccPortTxScheduledModeEnable
*/
PUBLIC IX_STATUS
ixAtmdAccPortTxScheduledModeEnablePararmsValidate (IxAtmLogicalPort port,
IxAtmdAccTxVcDemandUpdateCallback demandUpdate,
IxAtmdAccTxVcDemandClearCallback demandClear,
IxAtmdAccTxSchVcIdGetCallback vcIdGet)
{
IX_STATUS returnStatus = IX_SUCCESS;
/* check parameters */
if ((port >= IX_UTOPIA_MAX_PORTS) ||
(port < IX_UTOPIA_PORT_0) ||
(demandUpdate == NULL) ||
(demandClear == NULL) ||
(vcIdGet == NULL) ||
!ixAtmdAccPortConfigured (port))
{
returnStatus = IX_FAIL;
} /* end of if(port) */
return returnStatus;
}
