void gendsrav() { #ifdef INTERPRET_DSRAV gencallinterp((unsigned long)DSRAV, 0); #else int rt1, rt2, rd1, rd2; allocate_register_manually(ECX, (unsigned long *)dst->f.r.rs); rt1 = allocate_64_register1((unsigned long *)dst->f.r.rt); rt2 = allocate_64_register2((unsigned long *)dst->f.r.rt); rd1 = allocate_64_register1_w((unsigned long *)dst->f.r.rd); rd2 = allocate_64_register2_w((unsigned long *)dst->f.r.rd); if (rd1 != ECX && rd2 != ECX) { mov_reg32_reg32(rd1, rt1); mov_reg32_reg32(rd2, rt2); shrd_reg32_reg32_cl(rd1,rd2); sar_reg32_cl(rd2); test_reg32_imm32(ECX, 0x20); je_rj(5); mov_reg32_reg32(rd1, rd2); // 2 sar_reg32_imm8(rd2, 31); // 3 } else { int temp1, temp2; force_32(ECX); temp1 = lru_register(); temp2 = lru_register_exc1(temp1); free_register(temp1); free_register(temp2); mov_reg32_reg32(temp1, rt1); mov_reg32_reg32(temp2, rt2); shrd_reg32_reg32_cl(temp1, temp2); sar_reg32_cl(temp2); test_reg32_imm32(ECX, 0x20); je_rj(5); mov_reg32_reg32(temp1, temp2); // 2 sar_reg32_imm8(temp2, 31); // 3 mov_reg32_reg32(rd1, temp1); mov_reg32_reg32(rd2, temp2); } #endif }
void gendsrav(usf_state_t * state) { #ifdef INTERPRET_DSRAV gencallinterp(state, (unsigned int)state->current_instruction_table.DSRAV, 0); #else int rt1, rt2, rd1, rd2; allocate_register_manually(state, ECX, (unsigned int *)state->dst->f.r.rs); rt1 = allocate_64_register1(state, (unsigned int *)state->dst->f.r.rt); rt2 = allocate_64_register2(state, (unsigned int *)state->dst->f.r.rt); rd1 = allocate_64_register1_w(state, (unsigned int *)state->dst->f.r.rd); rd2 = allocate_64_register2_w(state, (unsigned int *)state->dst->f.r.rd); if (rd1 != ECX && rd2 != ECX) { mov_reg32_reg32(state, rd1, rt1); mov_reg32_reg32(state, rd2, rt2); shrd_reg32_reg32_cl(state, rd1,rd2); sar_reg32_cl(state, rd2); test_reg32_imm32(state, ECX, 0x20); je_rj(state, 5); mov_reg32_reg32(state, rd1, rd2); // 2 sar_reg32_imm8(state, rd2, 31); // 3 } else { int temp1, temp2; force_32(state, ECX); temp1 = lru_register(state); temp2 = lru_register_exc1(state, temp1); free_register(state, temp1); free_register(state, temp2); mov_reg32_reg32(state, temp1, rt1); mov_reg32_reg32(state, temp2, rt2); shrd_reg32_reg32_cl(state, temp1, temp2); sar_reg32_cl(state, temp2); test_reg32_imm32(state, ECX, 0x20); je_rj(state, 5); mov_reg32_reg32(state, temp1, temp2); // 2 sar_reg32_imm8(state, temp2, 31); // 3 mov_reg32_reg32(state, rd1, temp1); mov_reg32_reg32(state, rd2, temp2); } #endif }
void gendsrlv(void) { #ifdef INTERPRET_DSRLV gencallinterp((unsigned int)cached_interpreter_table.DSRLV, 0); #else int rt1, rt2, rd1, rd2; allocate_register_manually(ECX, (unsigned int *)dst->f.r.rs); rt1 = allocate_64_register1((unsigned int *)dst->f.r.rt); rt2 = allocate_64_register2((unsigned int *)dst->f.r.rt); rd1 = allocate_64_register1_w((unsigned int *)dst->f.r.rd); rd2 = allocate_64_register2_w((unsigned int *)dst->f.r.rd); if (rd1 != ECX && rd2 != ECX) { mov_reg32_reg32(rd1, rt1); mov_reg32_reg32(rd2, rt2); shrd_reg32_reg32_cl(rd1,rd2); shr_reg32_cl(rd2); test_reg32_imm32(ECX, 0x20); je_rj(4); mov_reg32_reg32(rd1, rd2); // 2 xor_reg32_reg32(rd2, rd2); // 2 } else { int temp1, temp2; force_32(ECX); temp1 = lru_register(); temp2 = lru_register_exc1(temp1); free_register(temp1); free_register(temp2); mov_reg32_reg32(temp1, rt1); mov_reg32_reg32(temp2, rt2); shrd_reg32_reg32_cl(temp1, temp2); shr_reg32_cl(temp2); test_reg32_imm32(ECX, 0x20); je_rj(4); mov_reg32_reg32(temp1, temp2); // 2 xor_reg32_reg32(temp2, temp2); // 2 mov_reg32_reg32(rd1, temp1); mov_reg32_reg32(rd2, temp2); } #endif }
void genbc1t_test(void) { test_m32_imm32((unsigned int*)&FCR31, 0x800000); je_rj(12); mov_m32_imm32((unsigned int*)(&branch_taken), 1); // 10 jmp_imm_short(10); // 2 mov_m32_imm32((unsigned int*)(&branch_taken), 0); // 10 }
void genbc1t_test() { test_m32_imm32((u32*)&FCR31, 0x800000); je_rj(12); mov_m32_imm32((u32*)(&branch_taken), 1); /* 10 */ jmp_imm_short(10); /* 2 */ mov_m32_imm32((u32*)(&branch_taken), 0); /* 10 */ }
static void genbc1t_test(void) { test_m32_imm32((unsigned int*)&(*r4300_cp1_fcr31()), 0x800000); je_rj(12); mov_m32_imm32((unsigned int*)(&g_dev.r4300.branch_taken), 1); // 10 jmp_imm_short(10); // 2 mov_m32_imm32((unsigned int*)(&g_dev.r4300.branch_taken), 0); // 10 }
static void genbc1t_test(void) { #if defined(__x86_64__) test_m32rel_imm32((uint32_t*)&FCR31, 0x800000); setne_m8rel((uint8_t *) &branch_taken); #else test_m32_imm32((uint32_t*)&FCR31, 0x800000); je_rj(12); mov_m32_imm32((uint32_t*)(&branch_taken), 1); // 10 jmp_imm_short(10); // 2 mov_m32_imm32((uint32_t*)(&branch_taken), 0); // 10 #endif }
void gendivu() { #ifdef INTERPRET_DIVU gencallinterp((unsigned long)DIVU, 0); #else int rs, rt; allocate_register_manually_w(EAX, (unsigned long *)&lo, 0); allocate_register_manually_w(EDX, (unsigned long *)&hi, 0); rs = allocate_register((unsigned long*)dst->f.r.rs); rt = allocate_register((unsigned long*)dst->f.r.rt); cmp_reg32_imm32(rt, 0); je_rj((rs == EAX ? 0 : 2) + 2 + 2); mov_reg32_reg32(EAX, rs); // 0 or 2 xor_reg32_reg32(EDX, EDX); // 2 div_reg32(rt); // 2 #endif }
void gendiv(void) { #ifdef INTERPRET_DIV gencallinterp((unsigned int)cached_interpreter_table.DIV, 0); #else int rs, rt; allocate_register_manually_w(EAX, (unsigned int *)&lo, 0); allocate_register_manually_w(EDX, (unsigned int *)&hi, 0); rs = allocate_register((unsigned int*)dst->f.r.rs); rt = allocate_register((unsigned int*)dst->f.r.rt); cmp_reg32_imm32(rt, 0); je_rj((rs == EAX ? 0 : 2) + 1 + 2); mov_reg32_reg32(EAX, rs); // 0 or 2 cdq(); // 1 idiv_reg32(rt); // 2 #endif }
void gendivu(usf_state_t * state) { #ifdef INTERPRET_DIVU gencallinterp(state, (unsigned int)state->current_instruction_table.DIVU, 0); #else int rs, rt; allocate_register_manually_w(state, EAX, (unsigned int *)&state->lo, 0); allocate_register_manually_w(state, EDX, (unsigned int *)&state->hi, 0); rs = allocate_register(state, (unsigned int*)state->dst->f.r.rs); rt = allocate_register(state, (unsigned int*)state->dst->f.r.rt); cmp_reg32_imm32(state, rt, 0); je_rj(state, (rs == EAX ? 0 : 2) + 2 + 2); mov_reg32_reg32(state, EAX, rs); // 0 or 2 xor_reg32_reg32(state, EDX, EDX); // 2 div_reg32(state, rt); // 2 #endif }
void gendivu(void) { #ifdef INTERPRET_DIVU gencallinterp((unsigned int)cached_interpreter_table.DIVU, 0); #else int rs, rt; allocate_register_manually_w(EAX, (unsigned int *)r4300_mult_lo(), 0); allocate_register_manually_w(EDX, (unsigned int *)r4300_mult_hi(), 0); rs = allocate_register((unsigned int*)g_dev.r4300.recomp.dst->f.r.rs); rt = allocate_register((unsigned int*)g_dev.r4300.recomp.dst->f.r.rt); cmp_reg32_imm32(rt, 0); je_rj((rs == EAX ? 0 : 2) + 2 + 2); mov_reg32_reg32(EAX, rs); // 0 or 2 xor_reg32_reg32(EDX, EDX); // 2 div_reg32(rt); // 2 #endif }
void gendivu(void) { #if defined(COUNT_INSTR) inc_m32abs(&instr_count[74]); #endif #ifdef INTERPRET_DIVU gencallinterp((unsigned long long)DIVU, 0); #else int rs, rt; allocate_register_32_manually_w(EAX, (unsigned int *)&lo); allocate_register_32_manually_w(EDX, (unsigned int *)&hi); rs = allocate_register_32((unsigned int*)dst->f.r.rs); rt = allocate_register_32((unsigned int*)dst->f.r.rt); cmp_reg32_imm32(rt, 0); je_rj((rs == EAX ? 0 : 2) + 2 + 2); mov_reg32_reg32(EAX, rs); // 0 or 2 xor_reg32_reg32(EDX, EDX); // 2 div_reg32(rt); // 2 #endif }
void gendiv(void) { #if defined(COUNT_INSTR) inc_m32rel(&instr_count[73]); #endif #ifdef INTERPRET_DIV gencallinterp((unsigned long long)cached_interpreter_table.DIV, 0); #else int rs, rt; allocate_register_32_manually_w(EAX, (unsigned int *)&lo); allocate_register_32_manually_w(EDX, (unsigned int *)&hi); rs = allocate_register_32((unsigned int*)dst->f.r.rs); rt = allocate_register_32((unsigned int*)dst->f.r.rt); cmp_reg32_imm32(rt, 0); je_rj((rs == EAX ? 0 : 2) + 1 + 2); mov_reg32_reg32(EAX, rs); // 0 or 2 cdq(); // 1 idiv_reg32(rt); // 2 #endif }