mali_error kbase_pm_powerup(kbase_device *kbdev)
{
unsigned long flags;
mali_error ret;
KBASE_DEBUG_ASSERT(kbdev != NULL);
mutex_lock(&kbdev->pm.lock);
/* A suspend won't happen during startup/insmod */
KBASE_DEBUG_ASSERT(!kbase_pm_is_suspending(kbdev));
/* Power up the GPU, don't enable IRQs as we are not ready to receive them. */
ret = kbase_pm_init_hw(kbdev, MALI_FALSE );
if (ret != MALI_ERROR_NONE) {
mutex_unlock(&kbdev->pm.lock);
return ret;
}
kbasep_pm_read_present_cores(kbdev);
kbdev->pm.debug_core_mask = kbdev->shader_present_bitmap;
/* Pretend the GPU is active to prevent a power policy turning the GPU cores off */
kbdev->pm.active_count = 1;
spin_lock_irqsave(&kbdev->pm.gpu_cycle_counter_requests_lock, flags);
/* Ensure cycle counter is off */
kbdev->pm.gpu_cycle_counter_requests = 0;
kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_COMMAND), GPU_COMMAND_CYCLE_COUNT_STOP, NULL);
spin_unlock_irqrestore(&kbdev->pm.gpu_cycle_counter_requests_lock, flags);
/* We are ready to receive IRQ's now as power policy is set up, so enable them now. */
#ifdef CONFIG_MALI_DEBUG
spin_lock_irqsave(&kbdev->pm.gpu_powered_lock, flags);
kbdev->pm.driver_ready_for_irqs = MALI_TRUE;
spin_unlock_irqrestore(&kbdev->pm.gpu_powered_lock, flags);
#endif
kbase_pm_enable_interrupts(kbdev);
/* Turn on the GPU and any cores needed by the policy */
kbase_pm_do_poweron(kbdev);
mutex_unlock(&kbdev->pm.lock);
/* Idle the GPU and/or cores, if the policy wants it to */
kbase_pm_context_idle(kbdev);
return MALI_ERROR_NONE;
}
mali_error kbase_pm_powerup(kbase_device *kbdev)
{
unsigned long flags;
mali_error ret;
OSK_ASSERT(kbdev != NULL);
ret = kbase_pm_init_hw(kbdev);
if (ret != MALI_ERROR_NONE)
{
return ret;
}
kbase_pm_power_transitioning(kbdev);
kbasep_pm_read_present_cores(kbdev);
/* Pretend the GPU is active to prevent a power policy turning the GPU cores off */
spin_lock_irqsave(&kbdev->pm.active_count_lock, flags);
kbdev->pm.active_count = 1;
spin_unlock_irqrestore(&kbdev->pm.active_count_lock, flags);
spin_lock_irqsave(&kbdev->pm.gpu_cycle_counter_requests_lock, flags);
/* Ensure cycle counter is off */
kbdev->pm.gpu_cycle_counter_requests = 0;
kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_COMMAND), GPU_COMMAND_CYCLE_COUNT_STOP, NULL);
spin_unlock_irqrestore(&kbdev->pm.gpu_cycle_counter_requests_lock, flags);
atomic_set(&kbdev->pm.pending_events, 0);
atomic_set(&kbdev->pm.work_active, KBASE_PM_WORK_ACTIVE_STATE_INACTIVE);
kbdev->pm.new_policy = NULL;
kbdev->pm.current_policy = policy_list[0];
KBASE_TRACE_ADD( kbdev, PM_CURRENT_POLICY_INIT, NULL, NULL, 0u, kbdev->pm.current_policy->id );
kbdev->pm.current_policy->init(kbdev);
kbase_pm_send_event(kbdev, KBASE_PM_EVENT_POLICY_INIT);
/* Idle the GPU */
kbase_pm_context_idle(kbdev);
return MALI_ERROR_NONE;
}
