hilinit()
{
register struct hilloop *hilp = &hil0; /* XXX */
register int i;
/*
* Initialize loop information
*/
hilp->hl_addr = HILADDR;
hilp->hl_cmdending = FALSE;
hilp->hl_actdev = hilp->hl_cmddev = 0;
hilp->hl_cmddone = FALSE;
hilp->hl_cmdbp = hilp->hl_cmdbuf;
hilp->hl_pollbp = hilp->hl_pollbuf;
hilp->hl_kbddev = 0;
hilp->hl_kbdlang = KBD_DEFAULT;
hilp->hl_kbdflags = 0;
/*
* Clear all queues and device associations with queues
*/
for (i = 0; i < NHILQ; i++) {
hilp->hl_queue[i].hq_eventqueue = NULL;
hilp->hl_queue[i].hq_procp = NULL;
hilp->hl_queue[i].hq_devmask = 0;
}
for (i = 0; i < NHILD; i++)
hilp->hl_device[i].hd_qmask = 0;
hilp->hl_device[HILLOOPDEV].hd_flags = (HIL_ALIVE|HIL_PSEUDO);
/*
* Reset the loop hardware, and collect keyboard/id info
*/
hilreset(hilp);
hilinfo(hilp);
kbdenable();
}
void
main(void)
{
cgapost(0);
mach0init();
options();
ioinit();
i8250console();
quotefmtinstall();
screeninit();
print("\nPlan 9\n");
trapinit0();
mmuinit0();
kbdinit();
i8253init();
cpuidentify();
meminit();
confinit();
archinit();
if(!isa20on())
panic("bootstrap didn't leave a20 address line enabled");
xinit();
if(i8237alloc != nil)
i8237alloc();
trapinit();
printinit();
cpuidprint();
mmuinit();
fpsavealloc();
if(arch->intrinit) /* launches other processors on an mp */
arch->intrinit();
timersinit();
mathinit();
kbdenable();
if(arch->clockenable)
arch->clockenable();
procinit0();
initseg();
if(delaylink){
bootlinks();
pcimatch(0, 0, 0);
}else
links();
conf.monitor = 1;
chandevreset();
cgapost(0xcd);
pageinit();
i8253link();
swapinit();
userinit();
active.thunderbirdsarego = 1;
cgapost(0x99);
schedinit();
}
int
itecngetc(dev_t dev)
{
int c;
/* XXX this should be moved */
kbdenable();
do {
c = kbdgetcn();
c = ite_cnfilter(c, ITEFILT_CONSOLE);
} while (c == -1);
return (c);
}
static void
kbdattach(device_t parent, device_t self, void *aux)
{
struct kbd_softc *sc = device_private(self);
struct mfp_softc *mfp = device_private(parent);
int s;
kbd_attached = 1;
s = spltty();
/* MFP interrupt #12 is for USART receive buffer full */
intio_intr_establish(mfp->sc_intr + 12, "kbd", kbdintr, sc);
sc->sc_softintr_cookie = softint_establish(SOFTINT_SERIAL,
kbdsoftint, sc);
kbdenable(1);
sc->sc_event_mode = 0;
sc->sc_events.ev_io = 0;
splx(s);
aprint_normal("\n");
}
void
main(u32int ax, u32int bx)
{
vlong hz;
memset(edata, 0, end - edata);
/*
* ilock via i8250enable via i8250console
* needs m->machno, sys->machptr[] set, and
* also 'up' set to nil.
*/
cgapost(sizeof(uintptr)*8);
memset(m, 0, sizeof(Mach));
m->machno = 0;
m->online = 1;
m->nixtype = NIXTC;
sys->machptr[m->machno] = &sys->mach;
m->stack = PTR2UINT(sys->machstk);
m->vsvm = sys->vsvmpage;
up = nil;
active.nonline = 1;
active.exiting = 0;
active.nbooting = 0;
asminit();
multiboot(ax, bx, 0);
options(oargc, oargv);
crapoptions();
/*
* Need something for initial delays
* until a timebase is worked out.
*/
m->cpuhz = 2000000000ll;
m->cpumhz = 2000;
cgainit();
i8250console("0");
consputs = cgaconsputs;
vsvminit(MACHSTKSZ, NIXTC);
conf.nmach = 1;
fmtinit();
print("\nNIX\n");
if(vflag){
print("&ax = %#p, ax = %#ux, bx = %#ux\n", &ax, ax, bx);
multiboot(ax, bx, vflag);
}
m->perf.period = 1;
if((hz = archhz()) != 0ll){
m->cpuhz = hz;
m->cyclefreq = hz;
m->cpumhz = hz/1000000ll;
}
/*
* Mmuinit before meminit because it
* flushes the TLB via m->pml4->pa.
*/
mmuinit();
ioinit();
kbdinit();
meminit();
confinit();
archinit();
mallocinit();
/*
* Acpiinit will cause the first malloc
* call to happen.
* If the system dies here it's probably due
* to malloc not being initialised
* correctly, or the data segment is misaligned
* (it's amazing how far you can get with
* things like that completely broken).
*/
acpiinit();
umeminit();
trapinit();
printinit();
/*
* This is necessary with GRUB and QEMU.
* Without it an interrupt can occur at a weird vector,
* because the vector base is likely different, causing
* havoc. Do it before any APIC initialisation.
*/
i8259init(32);
procinit0();
mpsinit(maxcores);
apiconline();
sipi();
timersinit();
kbdenable();
fpuinit();
psinit(conf.nproc);
initimage();
links();
devtabreset();
pageinit();
swapinit();
userinit();
nixsquids();
testiccs();
print("schedinit...\n");
schedinit();
}
/*
* at entry, l.s has set m for cpu0 and printed "Plan 9 from Be"
* but has not zeroed bss.
*/
void
main(void)
{
int cpu;
static ulong vfy = 0xcafebabe;
up = nil;
if (vfy != 0xcafebabe) {
serialputc('?');
serialputc('d');
panic("data segment misaligned");
}
memset(edata, 0, end - edata);
/*
* we can't lock until smpon has run, but we're supposed to wait
* until l1 & l2 are on. too bad. l1 is on, l2 will soon be.
*/
smpon();
iprint("ll Labs ");
cacheinit();
/*
* data segment is aligned, bss is zeroed, caches' characteristics
* are known. begin initialisation.
*/
mach0init();
l2pageinit();
mmuinit();
optionsinit("/boot/boot boot");
quotefmtinstall();
/* want plan9.ini to be able to affect memory sizing in confinit */
plan9iniinit(); /* before we step on plan9.ini in low memory */
/* l2 looks for *l2off= in plan9.ini */
l2cache->on(); /* l2->on requires locks to work, thus smpon */
l2cache->info(&cachel[2]);
allcache->on();
cortexa9cachecfg();
trapinit(); /* so confinit can probe memory to size it */
confinit(); /* figures out amount of memory */
/* xinit prints (if it can), so finish up the banner here. */
delay(100);
navailcpus = getncpus();
iprint("(mp arm; %d cpus)\n\n", navailcpus);
delay(100);
for (cpu = 1; cpu < navailcpus; cpu++)
stopcpu(cpu);
xinit();
irqtooearly = 0; /* now that xinit and trapinit have run */
mainmem->flags |= POOL_ANTAGONISM /* | POOL_PARANOIA */ ;
/*
* Printinit will cause the first malloc call.
* (printinit->qopen->malloc) unless any of the
* above (like clockinit) do an irqenable, which
* will call malloc.
* If the system dies here it's probably due
* to malloc(->xalloc) not being initialised
* correctly, or the data segment is misaligned
* (it's amazing how far you can get with
* things like that completely broken).
*
* (Should be) boilerplate from here on.
*/
archreset(); /* cfg clock signals, print cache cfg */
clockinit(); /* start clocks */
timersinit();
delay(50); /* let uart catch up */
printinit();
kbdenable();
cpuidprint();
chkmissing();
procinit0();
initseg();
// dmainit();
links();
conf.monitor = 1;
// screeninit();
iprint("pcireset...");
pcireset(); /* this tends to hang after a reboot */
iprint("ok\n");
chandevreset(); /* most devices are discovered here */
// i8250console(); /* too early; see init0 */
pageinit(); /* prints "1020M memory: ⋯ */
swapinit();
userinit();
/*
* starting a cpu will eventually result in it calling schedinit,
* so everything necessary to run user processes should be set up
* before starting secondary cpus.
*/
launchinit();
/* SMP & FW are already on when we get here; u-boot set them? */
for (cpu = 1; cpu < navailcpus; cpu++)
if (startcpu(cpu) < 0)
panic("cpu%d didn't start", cpu);
l1diag();
schedinit();
panic("cpu%d: schedinit returned", m->machno);
}
int
iteopen(dev_t dev, int mode, int devtype, struct lwp *l)
{
struct ite_softc *ip;
struct tty *tp;
int error, first, unit;
unit = ITEUNIT(dev);
first = 0;
if (unit >= ite_cd.cd_ndevs)
return ENXIO;
ip = getitesp(dev);
if (ip == NULL)
return ENXIO;
if ((ip->flags & ITE_ATTACHED) == 0)
return ENXIO;
if (ip->tp == NULL) {
tp = ip->tp = ttymalloc();
tty_attach(tp);
} else
tp = ip->tp;
if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp))
return (EBUSY);
if ((ip->flags & ITE_ACTIVE) == 0) {
ite_on(dev, 0);
first = 1;
}
tp->t_oproc = itestart;
tp->t_param = ite_param;
tp->t_dev = dev;
if ((tp->t_state & TS_ISOPEN) == 0 && tp->t_wopen == 0) {
ttychars(tp);
tp->t_iflag = TTYDEF_IFLAG;
tp->t_oflag = TTYDEF_OFLAG;
tp->t_cflag = TTYDEF_CFLAG;
tp->t_lflag = TTYDEF_LFLAG;
tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
tp->t_state = TS_CARR_ON;
ttsetwater(tp);
}
error = ttyopen(tp, 0, mode & O_NONBLOCK);
if (error)
goto bad;
error = tp->t_linesw->l_open(dev, tp);
if (error)
goto bad;
tp->t_winsize.ws_row = ip->rows;
tp->t_winsize.ws_col = ip->cols;
kbdenable();
return (0);
bad:
if (first)
ite_off(dev, 0);
return (error);
}
void
main(void)
{
Proc *savup;
static ulong vfy = Datamagic;
static char novga[] = "\nno vga; serial console only\n";
savup = up;
up = nil;
/* m has been set by l32v.s */
/*
* disable address wraps at 1MB boundaries.
* if we're 9boot, ldecomp.s already did this.
*/
a20init();
mach0init();
// options(); /* we don't get options passed to us */
ioinit();
/* we later call i8250console after plan9.ini has been read */
i8250config("0"); /* configure serial port 0 with defaults */
quotefmtinstall();
fmtinstall('i', eipfmt);
fmtinstall('I', eipfmt);
fmtinstall('E', eipfmt);
fmtinstall('V', eipfmt);
fmtinstall('M', eipfmt);
screeninit(); /* cga setup */
cgapost(0xc);
trapinit0();
mmuinit0();
kbdinit();
i8253init();
cpuidentify();
readlsconf();
meminit();
confinit();
archinit();
xinit();
if(i8237alloc != nil)
i8237alloc(); /* dma (for floppy) init */
trapinit();
printinit();
sanity();
cgapost(1);
/*
* soekris servers have no built-in video but each has a serial port.
* they must see serial output, if any, before cga output because
* otherwise the soekris bios will translate cga output to serial
* output, which will garble serial console output.
*/
pcimatch(nil, 0, 0); /* force scan of pci table */
if (!pcivga) {
screenputs = nil;
uartputs(novga, sizeof novga - 1);
}
print(" %s\n\n", hellomsg);
if (vfy != Datamagic)
panic("data segment incorrectly aligned or loaded");
if (savup)
print("up was non-nil (%#p) upon entry to main; bss wasn't zeroed!\n",
savup);
// xsummary();
cpuidprint();
mmuinit();
if(arch->intrinit) /* launches other processors on an mp */
arch->intrinit();
timersinit();
mathinit();
kbdenable();
/*
* 9loadusb runs much faster if we don't use the clock.
* perhaps we're competing with the bios for the use of it?
*/
if(!noclock && arch->clockenable)
arch->clockenable();
procinit0();
initseg();
if(delaylink){
bootlinks();
pcimatch(0, 0, 0);
}else
links();
conf.monitor = 1;
cgapost(0xcd);
chandevreset();
cgapost(2);
pageinit(); /* must follow xinit, and conf.mem must be populated */
i8253link();
userinit();
active.thunderbirdsarego = 1;
cgapost(0xb0);
schedinit();
}
void
main(void)
{
// int i;
extern char bdata[], edata[], end[], etext[];
static ulong vfy = 0xcafebabe;
/* l.s has already printed "Plan 9 from Be" */
// m = mach; /* now done in l.s */
/* realign data seg; apparently -H0 -R4096 does not pad the text seg */
if (vfy != 0xcafebabe) {
// wave('<'); wave('-');
memmove(bdata, etext, edata - bdata);
}
/*
* once data segment is in place, always zero bss since we may
* have been loaded by another Plan 9 kernel.
*/
memset(edata, 0, end - edata); /* zero BSS */
cacheuwbinv();
l2cacheuwbinv();
if (vfy != 0xcafebabe)
panic("data segment misaligned");
vfy = 0;
wave('l');
machinit();
mmuinit();
optionsinit("/boot/boot boot");
quotefmtinstall();
/* want plan9.ini to be able to affect memory sizing in confinit */
plan9iniinit(); /* before we step on plan9.ini in low memory */
trapinit(); /* so confinit can probe memory to size it */
confinit(); /* figures out amount of memory */
/* xinit prints (if it can), so finish up the banner here. */
delay(500);
iprint("l Labs\n\n");
delay(500);
xinit();
mainmem->flags |= POOL_ANTAGONISM /* | POOL_PARANOIA */ ;
/*
* Printinit will cause the first malloc call.
* (printinit->qopen->malloc) unless any of the
* above (like clockinit) do an irqenable, which
* will call malloc.
* If the system dies here it's probably due
* to malloc(->xalloc) not being initialised
* correctly, or the data segment is misaligned
* (it's amazing how far you can get with
* things like that completely broken).
*
* (Should be) boilerplate from here on.
*/
archreset(); /* configure clock signals */
clockinit(); /* start clocks */
timersinit();
watchdoginit();
delay(250); /* let uart catch up */
printinit();
kbdenable();
cpuidprint();
// chkmissing();
procinit0();
initseg();
dmainit();
links();
conf.monitor = 1;
screeninit();
chandevreset(); /* most devices are discovered here */
// i8250console(); /* too early; see init0 */
pageinit();
swapinit();
userinit();
schedinit();
}
