/* arch arm only */
static int kvmarm_try_push_interrupts(CPUState *env, struct kvm_run *run)
{
int r;
//gic_state *s = env->realviewgic_state.gic;
unsigned int irq;
if (run->ready_for_interrupt_injection &&
(env->interrupt_request & CPU_INTERRUPT_FIQ) )
{
irq = CPU_INTERRUPT_FIQ;
r = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &irq);
if (r < 0)
printf("cpu %d fail inject %x\n", env->cpu_index, irq);
env->exit_request = 1;
}
//else if (kvm_is_ready_for_interrupt_injection(env->kvm_cpu_state.vcpu_ctx) &&
else if( (env->interrupt_request & CPU_INTERRUPT_HARD))
{
irq = CPU_INTERRUPT_HARD;
r = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &irq);
if (r < 0)
printf("cpu %d fail inject %x\n", env->cpu_index, irq);
env->exit_request = 1;
}
return 0;
}
static int kvm_arch_sync_sregs(PowerPCCPU *cpu)
{
CPUPPCState *cenv = &cpu->env;
CPUState *cs = CPU(cpu);
struct kvm_sregs sregs;
int ret;
if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
/* What we're really trying to say is "if we're on BookE, we use
the native PVR for now". This is the only sane way to check
it though, so we potentially confuse users that they can run
BookE guests on BookS. Let's hope nobody dares enough :) */
return 0;
} else {
if (!cap_segstate) {
fprintf(stderr, "kvm error: missing PVR setting capability\n");
return -ENOSYS;
}
}
ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs);
if (ret) {
return ret;
}
sregs.pvr = cenv->spr[SPR_PVR];
return kvm_vcpu_ioctl(cs, KVM_SET_SREGS, &sregs);
}
int kvm_arch_get_registers(CPUState *env)
{
struct kvm_regs regs;
struct kvm_sregs sregs;
uint32_t i, ret;
ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s);
if (ret < 0)
return ret;
ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
if (ret < 0)
return ret;
env->ctr = regs.ctr;
env->lr = regs.lr;
env->xer = regs.xer;
env->msr = regs.msr;
env->nip = regs.pc;
env->spr[SPR_SRR0] = regs.srr0;
env->spr[SPR_SRR1] = regs.srr1;
env->spr[SPR_SPRG0] = regs.sprg0;
env->spr[SPR_SPRG1] = regs.sprg1;
env->spr[SPR_SPRG2] = regs.sprg2;
env->spr[SPR_SPRG3] = regs.sprg3;
env->spr[SPR_SPRG4] = regs.sprg4;
env->spr[SPR_SPRG5] = regs.sprg5;
env->spr[SPR_SPRG6] = regs.sprg6;
env->spr[SPR_SPRG7] = regs.sprg7;
for (i = 0; i < 32; i++)
env->gpr[i] = regs.gpr[i];
#ifdef KVM_CAP_PPC_SEGSTATE
if (kvm_check_extension(env->kvm_state, KVM_CAP_PPC_SEGSTATE)) {
env->sdr1 = sregs.u.s.sdr1;
/* Sync SLB */
#ifdef TARGET_PPC64
for (i = 0; i < 64; i++) {
ppc_store_slb(env, sregs.u.s.ppc64.slb[i].slbe,
sregs.u.s.ppc64.slb[i].slbv);
}
#endif
/* Sync SRs */
for (i = 0; i < 16; i++) {
env->sr[i] = sregs.u.s.ppc32.sr[i];
}
/* Sync BATs */
for (i = 0; i < 8; i++) {
env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff;
env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32;
env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff;
env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32;
}
}
void kvm_show_code(CPUState *env)
{
#define SHOW_CODE_LEN 50
struct kvm_regs regs;
struct kvm_sregs sregs;
int r, n;
int back_offset;
unsigned char code;
char code_str[SHOW_CODE_LEN * 3 + 1];
unsigned long rip;
r = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
if (r < 0 ) {
perror("KVM_GET_SREGS");
return;
}
r = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s);
if (r < 0) {
perror("KVM_GET_REGS");
return;
}
rip = sregs.cs.base + regs.rip;
back_offset = regs.rip;
if (back_offset > 20)
back_offset = 20;
*code_str = 0;
for (n = -back_offset; n < SHOW_CODE_LEN-back_offset; ++n) {
if (n == 0)
strcat(code_str, " -->");
cpu_physical_memory_rw(rip + n, &code, 1, 1);
sprintf(code_str + strlen(code_str), " %02x", code);
}
fprintf(stderr, "code:%s\n", code_str);
}
static int kvm_put_vpa(CPUState *cs)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
CPUPPCState *env = &cpu->env;
struct kvm_one_reg reg;
int ret;
/* SLB shadow or DTL can't be registered unless a master VPA is
* registered. That means when restoring state, if a VPA *is*
* registered, we need to set that up first. If not, we need to
* deregister the others before deregistering the master VPA */
assert(env->vpa_addr || !(env->slb_shadow_addr || env->dtl_addr));
if (env->vpa_addr) {
reg.id = KVM_REG_PPC_VPA_ADDR;
reg.addr = (uintptr_t)&env->vpa_addr;
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
if (ret < 0) {
dprintf("Unable to set VPA address to KVM: %s\n", strerror(errno));
return ret;
}
}
assert((uintptr_t)&env->slb_shadow_size
== ((uintptr_t)&env->slb_shadow_addr + 8));
reg.id = KVM_REG_PPC_VPA_SLB;
reg.addr = (uintptr_t)&env->slb_shadow_addr;
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
if (ret < 0) {
dprintf("Unable to set SLB shadow state to KVM: %s\n", strerror(errno));
return ret;
}
assert((uintptr_t)&env->dtl_size == ((uintptr_t)&env->dtl_addr + 8));
reg.id = KVM_REG_PPC_VPA_DTL;
reg.addr = (uintptr_t)&env->dtl_addr;
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
if (ret < 0) {
dprintf("Unable to set dispatch trace log state to KVM: %s\n",
strerror(errno));
return ret;
}
if (!env->vpa_addr) {
reg.id = KVM_REG_PPC_VPA_ADDR;
reg.addr = (uintptr_t)&env->vpa_addr;
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
if (ret < 0) {
dprintf("Unable to set VPA address to KVM: %s\n", strerror(errno));
return ret;
}
}
return 0;
}
int kvm_inject_irq(CPUState *env, unsigned irq)
{
struct kvm_interrupt intr;
intr.irq = irq;
return kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
}
/* S390CPUClass::initial_reset() */
static void s390_cpu_initial_reset(CPUState *s)
{
S390CPU *cpu = S390_CPU(s);
CPUS390XState *env = &cpu->env;
s390_cpu_reset(s);
/* initial reset does not touch regs,fregs and aregs */
memset(&env->fpc, 0, offsetof(CPUS390XState, cpu_num) -
offsetof(CPUS390XState, fpc));
/* architectured initial values for CR 0 and 14 */
env->cregs[0] = CR0_RESET;
env->cregs[14] = CR14_RESET;
env->pfault_token = -1UL;
#if defined(CONFIG_KVM)
/* Reset state inside the kernel that we cannot access yet from QEMU. */
if (kvm_enabled()) {
if (kvm_vcpu_ioctl(s, KVM_S390_INITIAL_RESET, NULL)) {
perror("Initial CPU reset failed");
}
}
#endif
}
static void kvm_sw_tlb_put(PowerPCCPU *cpu)
{
CPUPPCState *env = &cpu->env;
CPUState *cs = CPU(cpu);
struct kvm_dirty_tlb dirty_tlb;
unsigned char *bitmap;
int ret;
if (!env->kvm_sw_tlb) {
return;
}
bitmap = g_malloc((env->nb_tlb + 7) / 8);
memset(bitmap, 0xFF, (env->nb_tlb + 7) / 8);
dirty_tlb.bitmap = (uintptr_t)bitmap;
dirty_tlb.num_dirty = env->nb_tlb;
ret = kvm_vcpu_ioctl(cs, KVM_DIRTY_TLB, &dirty_tlb);
if (ret) {
fprintf(stderr, "%s: KVM_DIRTY_TLB: %s\n",
__func__, strerror(-ret));
}
g_free(bitmap);
}
int kvm_put_vcpu_events(CPUState *env)
{
#ifdef KVM_CAP_VCPU_EVENTS
struct kvm_vcpu_events events;
if (!kvm_has_vcpu_events()) {
return 0;
}
events.exception.injected = (env->exception_injected >= 0);
events.exception.nr = env->exception_injected;
events.exception.has_error_code = env->has_error_code;
events.exception.error_code = env->error_code;
events.interrupt.injected = (env->interrupt_injected >= 0);
events.interrupt.nr = env->interrupt_injected;
events.interrupt.soft = env->soft_interrupt;
events.nmi.injected = env->nmi_injected;
events.nmi.pending = env->nmi_pending;
events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
events.sipi_vector = env->sipi_vector;
events.flags =
KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
#else
return 0;
#endif
}
int kvm_arch_get_registers(CPUState *env)
{
struct kvm_regs regs;
int i, ret;
ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s);
if (ret < 0)
return ret;
env->uncached_cpsr =regs.cpsr;
env->spsr = regs.spsr;
/*****synchronize CP15*******/
env->cp15.c0_cpuid = regs.cp15.c0_cpuid;
env->cp15.c0_cachetype = regs.cp15.c0_cachetype;
for(i=0;i<16;i++)
env->cp15.c0_ccsid[i] = regs.cp15.c0_ccsid[i];
env->cp15.c0_clid = regs.cp15.c0_clid;
env->cp15.c0_cssel = regs.cp15.c0_cssel;
for(i=0;i<8;i++)
env->cp15.c0_c1[i] = regs.cp15.c0_c1[i];
for(i=0;i<8;i++)
env->cp15.c0_c2[i] = regs.cp15.c0_c2[i];
env->cp15.c1_sys = regs.cp15.c1_sys;
env->cp15.c1_coproc = regs.cp15.c1_coproc;
env->cp15.c1_xscaleauxcr = regs.cp15.c1_xscaleauxcr;
env->cp15.c2_base0 = regs.cp15.c2_base0;
env->cp15.c2_base1 = regs.cp15.c2_base1;
env->cp15.c2_control = regs.cp15.c2_control;
env->cp15.c2_mask = regs.cp15.c2_mask;
env->cp15.c2_base_mask = regs.cp15.c2_base_mask;
env->cp15.c2_data = regs.cp15.c2_data;
env->cp15.c2_insn = regs.cp15.c2_insn;
env->cp15.c3 = regs.cp15.c3;
env->cp15.c5_insn = regs.cp15.c5_insn;
env->cp15.c5_data = regs.cp15.c5_data;
for(i=0;i<8;i++)
env->cp15.c6_region[i] = regs.cp15.c6_region[i];
env->cp15.c6_insn = regs.cp15.c6_insn;
env->cp15.c6_data = regs.cp15.c6_data;
env->cp15.c9_insn = regs.cp15.c9_insn;
env->cp15.c9_data = regs.cp15.c9_data;
env->cp15.c13_fcse = regs.cp15.c13_fcse;
env->cp15.c13_context = regs.cp15.c13_context;
env->cp15.c13_tls1 = regs.cp15.c13_tls1;
env->cp15.c13_tls2 = regs.cp15.c13_tls2;
env->cp15.c13_tls3 = regs.cp15.c13_tls3;
env->cp15.c15_cpar = regs.cp15.c15_cpar;
env->cp15.c15_ticonfig = regs.cp15.c15_ticonfig;
env->cp15.c15_i_max = regs.cp15.c15_i_max;
env->cp15.c15_i_min = regs.cp15.c15_i_min;
env->cp15.c15_threadid = regs.cp15.c15_threadid;
/*******************************************************************/
for (i = 0;i < 16; i++){
env->regs[i] = regs.gpr[i];
}
return 0;
}
int kvm_enable_vapic(CPUState *env, uint64_t vapic)
{
struct kvm_vapic_addr va = {
.vapic_addr = vapic,
};
return kvm_vcpu_ioctl(env, KVM_SET_VAPIC_ADDR, &va);
}
int kvm_inject_nmi(CPUState *env)
{
#ifdef KVM_CAP_USER_NMI
return kvm_vcpu_ioctl(env, KVM_NMI);
#else
return -ENOSYS;
#endif
}
int kvm_set_mce(CPUState *env, struct kvm_x86_mce *m)
{
#ifdef KVM_CAP_MCE
return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, m);
#else
return -ENOSYS;
#endif
}
int kvm_trigger_irq(void)
{
unsigned irq = KVM_INTERRUPT_SET;
kvm_vcpu_ioctl(KVM_INTERRUPT, &irq);
return 0;
}
int kvm_setup_mce(CPUState *env, uint64_t *mcg_cap)
{
#ifdef KVM_CAP_MCE
return kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, mcg_cap);
#else
return -ENOSYS;
#endif
}
void molcpu_mainloop( void )
{
static int inited = 0;
if (!inited) {
inited = 1;
kvm_regs_mol2kvm();
start_alarm();
}
while (1) {
int r;
int (*osicall)(int);
if (mregs->interrupt) {
if(mainloop_interrupt(0)) {
printf("mainloop_interrupt wants us to exit the main loop\n");
return;
}
}
mregs->in_virtual_mode = 1;
r = kvm_vcpu_ioctl(KVM_RUN, 0);
mregs->in_virtual_mode = 0;
if (r == -EINTR || r == -EAGAIN) {
osicall = gRVECtable[RVEC_TIMER].rvec;
osicall(0);
continue;
}
switch (kvm_run->exit_reason) {
case KVM_EXIT_MMIO:
kvm_do_mmio();
break;
case KVM_EXIT_OSI:
{
__u64 *gprs = kvm_run->osi.gprs;
int i;
for (i = 0; i < 32; i++)
mregs->gpr[i] = gprs[i];
osicall = gRVECtable[RVEC_OSI_SYSCALL].rvec;
osicall(0);
for (i = 0; i < 32; i++)
gprs[i] = mregs->gpr[i];
break;
}
default:
fprintf(stderr, "KVM: Unknown exit code: %d\n",
kvm_run->exit_reason);
exit(1);
break;
}
}
}
int kvm_arch_put_registers(CPUState *env, int level)
{
struct kvm_regs regs;
int ret;
int i;
ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s);
if (ret < 0)
return ret;
regs.ctr = env->ctr;
regs.lr = env->lr;
regs.xer = env->xer;
regs.msr = env->msr;
regs.pc = env->nip;
regs.srr0 = env->spr[SPR_SRR0];
regs.srr1 = env->spr[SPR_SRR1];
regs.sprg0 = env->spr[SPR_SPRG0];
regs.sprg1 = env->spr[SPR_SPRG1];
regs.sprg2 = env->spr[SPR_SPRG2];
regs.sprg3 = env->spr[SPR_SPRG3];
regs.sprg4 = env->spr[SPR_SPRG4];
regs.sprg5 = env->spr[SPR_SPRG5];
regs.sprg6 = env->spr[SPR_SPRG6];
regs.sprg7 = env->spr[SPR_SPRG7];
regs.pid = env->spr[SPR_BOOKE_PID];
for (i = 0;i < 32; i++)
regs.gpr[i] = env->gpr[i];
ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, ®s);
if (ret < 0)
return ret;
if (env->tlb_dirty) {
kvm_sw_tlb_put(env);
env->tlb_dirty = false;
}
return ret;
}
int kvm_arch_init_vcpu(CPUState *cenv)
{
int ret = 0;
struct kvm_sregs sregs;
sregs.pvr = cenv->spr[SPR_PVR];
ret = kvm_vcpu_ioctl(cenv, KVM_SET_SREGS, &sregs);
return ret;
}
int kvm_set_mpstate(CPUState *env, struct kvm_mp_state *mp_state)
{
int r;
r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_MP_STATE);
if (r > 0) {
return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, mp_state);
}
return -ENOSYS;
}
static void kvmclock_vm_state_change(void *opaque, int running,
RunState state)
{
KVMClockState *s = opaque;
CPUState *cpu = first_cpu;
int cap_clock_ctrl = kvm_check_extension(kvm_state, KVM_CAP_KVMCLOCK_CTRL);
int ret;
if (running) {
struct kvm_clock_data data;
s->clock_valid = false;
data.clock = s->clock;
data.flags = 0;
ret = kvm_vm_ioctl(kvm_state, KVM_SET_CLOCK, &data);
if (ret < 0) {
fprintf(stderr, "KVM_SET_CLOCK failed: %s\n", strerror(ret));
abort();
}
if (!cap_clock_ctrl) {
return;
}
for (cpu = first_cpu; cpu != NULL; cpu = cpu->next_cpu) {
ret = kvm_vcpu_ioctl(cpu, KVM_KVMCLOCK_CTRL, 0);
if (ret) {
if (ret != -EINVAL) {
fprintf(stderr, "%s: %s\n", __func__, strerror(-ret));
}
return;
}
}
} else {
struct kvm_clock_data data;
int ret;
if (s->clock_valid) {
return;
}
ret = kvm_vm_ioctl(kvm_state, KVM_GET_CLOCK, &data);
if (ret < 0) {
fprintf(stderr, "KVM_GET_CLOCK failed: %s\n", strerror(ret));
abort();
}
s->clock = data.clock;
/*
* If the VM is stopped, declare the clock state valid to
* avoid re-reading it on next vmsave (which would return
* a different value). Will be reset when the VM is continued.
*/
s->clock_valid = true;
}
}
void kvm_show_regs(CPUState *env)
{
struct kvm_regs regs;
struct kvm_sregs sregs;
int r;
r = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s);
if (r < 0) {
perror("KVM_GET_REGS");
return;
}
fprintf(stderr,
"rax %016llx rbx %016llx rcx %016llx rdx %016llx\n"
"rsi %016llx rdi %016llx rsp %016llx rbp %016llx\n"
"r8 %016llx r9 %016llx r10 %016llx r11 %016llx\n"
"r12 %016llx r13 %016llx r14 %016llx r15 %016llx\n"
"rip %016llx rflags %08llx\n",
regs.rax, regs.rbx, regs.rcx, regs.rdx,
regs.rsi, regs.rdi, regs.rsp, regs.rbp,
regs.r8, regs.r9, regs.r10, regs.r11,
regs.r12, regs.r13, regs.r14, regs.r15,
regs.rip, regs.rflags);
r = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
if (r < 0) {
perror("KVM_GET_SREGS");
return;
}
print_seg(stderr, "cs", &sregs.cs);
print_seg(stderr, "ds", &sregs.ds);
print_seg(stderr, "es", &sregs.es);
print_seg(stderr, "ss", &sregs.ss);
print_seg(stderr, "fs", &sregs.fs);
print_seg(stderr, "gs", &sregs.gs);
print_seg(stderr, "tr", &sregs.tr);
print_seg(stderr, "ldt", &sregs.ldt);
print_dt(stderr, "gdt", &sregs.gdt);
print_dt(stderr, "idt", &sregs.idt);
fprintf(stderr, "cr0 %llx cr2 %llx cr3 %llx cr4 %llx cr8 %llx"
" efer %llx\n",
sregs.cr0, sregs.cr2, sregs.cr3, sregs.cr4, sregs.cr8,
sregs.efer);
}
int kvm_openpic_connect_vcpu(DeviceState *d, CPUState *cs)
{
KVMOpenPICState *opp = KVM_OPENPIC(d);
struct kvm_enable_cap encap = {};
encap.cap = KVM_CAP_IRQ_MPIC;
encap.args[0] = opp->fd;
encap.args[1] = cs->cpu_index;
return kvm_vcpu_ioctl(cs, KVM_ENABLE_CAP, &encap);
}
int kvm_set_msrs(CPUState *env, struct kvm_msr_entry *msrs, int n)
{
struct kvm_msrs *kmsrs = qemu_malloc(sizeof *kmsrs + n * sizeof *msrs);
int r;
kmsrs->nmsrs = n;
memcpy(kmsrs->entries, msrs, n * sizeof *msrs);
r = kvm_vcpu_ioctl(env, KVM_SET_MSRS, kmsrs);
free(kmsrs);
return r;
}
int kvm_get_lapic(CPUState *env, struct kvm_lapic_state *s)
{
int r = 0;
if (!kvm_irqchip_in_kernel())
return r;
r = kvm_vcpu_ioctl(env, KVM_GET_LAPIC, s);
if (r < 0)
fprintf(stderr, "KVM_GET_LAPIC failed\n");
return r;
}
static int kvm_get_vpa(CPUState *cs)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
CPUPPCState *env = &cpu->env;
struct kvm_one_reg reg;
int ret;
reg.id = KVM_REG_PPC_VPA_ADDR;
reg.addr = (uintptr_t)&env->vpa_addr;
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
if (ret < 0) {
dprintf("Unable to get VPA address from KVM: %s\n", strerror(errno));
return ret;
}
assert((uintptr_t)&env->slb_shadow_size
== ((uintptr_t)&env->slb_shadow_addr + 8));
reg.id = KVM_REG_PPC_VPA_SLB;
reg.addr = (uintptr_t)&env->slb_shadow_addr;
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
if (ret < 0) {
dprintf("Unable to get SLB shadow state from KVM: %s\n",
strerror(errno));
return ret;
}
assert((uintptr_t)&env->dtl_size == ((uintptr_t)&env->dtl_addr + 8));
reg.id = KVM_REG_PPC_VPA_DTL;
reg.addr = (uintptr_t)&env->dtl_addr;
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
if (ret < 0) {
dprintf("Unable to get dispatch trace log state from KVM: %s\n",
strerror(errno));
return ret;
}
return 0;
}
static int __kvm_init(void)
{
struct kvm_sregs sregs;
memset(&sregs, 0, sizeof(sregs));
sregs.pvr = mregs->spr[S_PVR];
if (kvm_vcpu_ioctl(KVM_SET_SREGS, &sregs)) {
fprintf(stderr, "KVM sregs failed\n");
return -1;
}
return 0;
}
int kvm_setup_cpuid2(CPUState *env, int nent,
struct kvm_cpuid_entry2 *entries)
{
struct kvm_cpuid2 *cpuid;
int r;
cpuid = qemu_malloc(sizeof(*cpuid) + nent * sizeof(*entries));
cpuid->nent = nent;
memcpy(cpuid->entries, entries, nent * sizeof(*entries));
r = kvm_vcpu_ioctl(env, KVM_SET_CPUID2, cpuid);
free(cpuid);
return r;
}
void kvm_regs_mol2kvm(void)
{
struct kvm_regs regs;
int i, ret;
ret = kvm_vcpu_ioctl(KVM_GET_REGS, ®s);
if (ret < 0)
return;
regs.pc = mregs->nip;
regs.msr = mregs->msr;
regs.lr = mregs->link;
regs.cr = mregs->cr;
regs.ctr = mregs->ctr;
regs.xer = mregs->xer;
for (i = 0; i < 32; i++)
regs.gpr[i] = mregs->gpr[i];
ret = kvm_vcpu_ioctl(KVM_SET_REGS, ®s);
return;
}
int kvm_init(void)
{
long mmap_size;
struct kvm_enable_cap cap;
int r;
kvm_fd = open("/dev/kvm", O_RDWR);
if (kvm_fd < 0) {
fprintf(stderr, "KVM: Couldn't open /dev/kvm\n");
return -1;
}
vm_fd = kvm_ioctl(KVM_CREATE_VM, 0);
if (vm_fd < 0) {
fprintf(stderr, "KVM: Couldn't create VM\n");
return -1;
}
vcpu_fd = kvm_vm_ioctl(KVM_CREATE_VCPU, 0);
if (vcpu_fd < 0) {
fprintf(stderr, "kvm_create_vcpu failed\n");
return -1;
}
memset(&cap, 0, sizeof(cap));
cap.cap = KVM_CAP_PPC_OSI;
r = kvm_vcpu_ioctl(KVM_ENABLE_CAP, &cap);
if (r < 0) {
fprintf(stderr, "kvm_enable_cap failed\n");
return -1;
}
mmap_size = kvm_ioctl(KVM_GET_VCPU_MMAP_SIZE, 0);
if (mmap_size < 0) {
fprintf(stderr, "KVM_GET_VCPU_MMAP_SIZE failed\n");
return -1;
}
kvm_run = (struct kvm_run *)mmap(NULL, mmap_size, PROT_READ | PROT_WRITE,
MAP_SHARED, vcpu_fd, 0);
if (kvm_run == MAP_FAILED) {
fprintf(stderr, "mmap'ing vcpu state failed\n");
return -1;
}
return 0;
}
/* Set up a shared TLB array with KVM */
static int kvm_booke206_tlb_init(PowerPCCPU *cpu)
{
CPUPPCState *env = &cpu->env;
CPUState *cs = CPU(cpu);
struct kvm_book3e_206_tlb_params params = {};
struct kvm_config_tlb cfg = {};
struct kvm_enable_cap encap = {};
unsigned int entries = 0;
int ret, i;
if (!kvm_enabled() ||
!kvm_check_extension(cs->kvm_state, KVM_CAP_SW_TLB)) {
return 0;
}
assert(ARRAY_SIZE(params.tlb_sizes) == BOOKE206_MAX_TLBN);
for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
params.tlb_sizes[i] = booke206_tlb_size(env, i);
params.tlb_ways[i] = booke206_tlb_ways(env, i);
entries += params.tlb_sizes[i];
}
assert(entries == env->nb_tlb);
assert(sizeof(struct kvm_book3e_206_tlb_entry) == sizeof(ppcmas_tlb_t));
env->tlb_dirty = true;
cfg.array = (uintptr_t)env->tlb.tlbm;
cfg.array_len = sizeof(ppcmas_tlb_t) * entries;
cfg.params = (uintptr_t)¶ms;
cfg.mmu_type = KVM_MMU_FSL_BOOKE_NOHV;
encap.cap = KVM_CAP_SW_TLB;
encap.args[0] = (uintptr_t)&cfg;
ret = kvm_vcpu_ioctl(cs, KVM_ENABLE_CAP, &encap);
if (ret < 0) {
fprintf(stderr, "%s: couldn't enable KVM_CAP_SW_TLB: %s\n",
__func__, strerror(-ret));
return ret;
}
env->kvm_sw_tlb = true;
return 0;
}
