static void whc_hw_init_dn_buf(struct whc *whc) { /* Clear the Device Notification buffer to ensure the V (valid) * bits are clear. */ memset(whc->dn_buf, 0, 4096); le_writeq(whc->dn_buf_dma, whc->base + WUSBDNTSBUFADDR); }
static void whc_hw_init_di_buf(struct whc *whc) { int d; /* Disable all entries in the Device Information buffer. */ for (d = 0; d < whc->n_devices; d++) whc->di_buf[d].addr_sec_info = WHC_DI_DISABLE; le_writeq(whc->di_buf_dma, whc->base + WUSBDEVICEINFOADDR); }
static void whc_hw_init_di_buf(struct whc *whc) { int d; for (d = 0; d < whc->n_devices; d++) whc->di_buf[d].addr_sec_info = WHC_DI_DISABLE; le_writeq(whc->di_buf_dma, whc->base + WUSBDEVICEINFOADDR); }
/** * Reset event reception mechanism and tell hw we are ready to get more * * We have read all the events in the event buffer, so we are ready to * reset it to the beginning. * * This is only called during initialization or after an event buffer * has been retired. This means we can be sure that event processing * is disabled and it's safe to update the URCEVTADDR register. * * There's no need to wait for the event processing to start as the * URC will not clear URCCMD_ACTIVE until (internal) event buffer * space is available. */ static void whcrc_enable_events(struct whcrc *whcrc) { u32 urccmd; le_writeq(whcrc->evt_dma_buf, whcrc->rc_base + URCEVTADDR); spin_lock(&whcrc->irq_lock); urccmd = le_readl(whcrc->rc_base + URCCMD) & ~URCCMD_ACTIVE; le_writel(urccmd | URCCMD_EARV, whcrc->rc_base + URCCMD); spin_unlock(&whcrc->irq_lock); }
/** * Execute an UWB RC command on WHCI/RC * * @rc: Instance of a Radio Controller that is a whcrc * @cmd: Buffer containing the RCCB and payload to execute * @cmd_size: Size of the command buffer. * * We copy the command into whcrc->cmd_buf (as it is pretty and * aligned`and physically contiguous) and then press the right keys in * the controller's URCCMD register to get it to read it. We might * have to wait for the cmd_sem to be open to us. * * NOTE: rc's mutex has to be locked */ static int whcrc_cmd(struct uwb_rc *uwb_rc, const struct uwb_rccb *cmd, size_t cmd_size) { int result = 0; struct whcrc *whcrc = uwb_rc->priv; struct device *dev = &whcrc->umc_dev->dev; u32 urccmd; if (cmd_size >= 4096) return -EINVAL; /* * If the URC is halted, then the hardware has reset itself. * Attempt to recover by restarting the device and then return * an error as it's likely that the current command isn't * valid for a newly started RC. */ if (le_readl(whcrc->rc_base + URCSTS) & URCSTS_HALTED) { dev_err(dev, "requesting reset of halted radio controller\n"); uwb_rc_reset_all(uwb_rc); return -EIO; } result = wait_event_timeout(whcrc->cmd_wq, !(le_readl(whcrc->rc_base + URCCMD) & URCCMD_ACTIVE), HZ/2); if (result == 0) { dev_err(dev, "device is not ready to execute commands\n"); return -ETIMEDOUT; } memmove(whcrc->cmd_buf, cmd, cmd_size); le_writeq(whcrc->cmd_dma_buf, whcrc->rc_base + URCCMDADDR); spin_lock(&whcrc->irq_lock); urccmd = le_readl(whcrc->rc_base + URCCMD); urccmd &= ~(URCCMD_EARV | URCCMD_SIZE_MASK); le_writel(urccmd | URCCMD_ACTIVE | URCCMD_IWR | cmd_size, whcrc->rc_base + URCCMD); spin_unlock(&whcrc->irq_lock); return 0; }
static void whc_hw_init_dn_buf(struct whc *whc) { memset(whc->dn_buf, 0, 4096); le_writeq(whc->dn_buf_dma, whc->base + WUSBDNTSBUFADDR); }