static void switch_control_test_fsw_func(switch_control_t *sc)
{
/* Turn light on when switch state goes low. */
static uint32_t left_toggle, right_toggle;
uint32_t data = *((uint32_t*)sc->data);
switch (data) {
case 1:
if (switch_control_get_state(sc)) {
left_toggle ^= 0x1;
switch_control_set_state(sc,0x0);
}
break;
case 2:
if (switch_control_get_state(sc)) {
right_toggle ^= 0x1;
switch_control_set_state(sc,0x0);
}
break;
}
if (left_toggle) {
led1_reset();
led3_set();
} else {
led1_set();
led3_reset();
}
if (right_toggle) {
led5_reset();
led7_set();
} else {
led5_set();
led7_reset();
}
}
static void switch_control_test_func(switch_control_t *sc)
{
/* Turn light on when switch state goes low. */
uint32_t data = *((uint32_t*)sc->data);
switch (data) {
case 1:
if (!switch_control_get_state(sc)) {
led1_set();
} else {
led1_reset();
}
break;
case 3:
if (!switch_control_get_state(sc)) {
led3_set();
} else {
led3_reset();
}
break;
case 5:
if (!switch_control_get_state(sc)) {
led5_set();
} else {
led5_reset();
}
break;
case 7:
if (!switch_control_get_state(sc)) {
led7_set();
} else {
led7_reset();
}
break;
}
}
void led_status_update(void)
{
if (synth_control_get_recordState()) {
led1_set();
} else {
led1_reset();
}
if (synth_control_get_schedulerState()) {
led3_set();
} else {
led3_reset();
}
if (synth_control_get_feedbackState()) {
led5_set();
} else {
led5_reset();
}
}
int main(void)
{
portBASE_TYPE ret = 0;
unsigned int v=0;
ddk_init();
// call HW function tests and FPGA ROM programming. This will program the FPGA bitstream
// into flash ROM if FPGA is uninitialized.
hw_test_main();
led1_clr();
led2_clr();
led3_clr();
led4_clr();
// error
while(g_test_done != 1) {
led1_set();
led2_set();
led3_set();
led4_set();
ddk_delay(50000);
led1_clr();
led2_clr();
led3_clr();
led4_clr();
ddk_delay(50000);
}
puts("[*] init done.");
ret = xTaskCreate( vBlinkTask,
_STR "BLINK",
mainBASIC_BLINK_STACK_SIZE,
( void * ) NULL,
tskIDLE_PRIORITY,
&task_handles[TASK_BLINK_MAIN]
);
if(ret != pdTRUE)
for(;;);
/*
ret = xTaskCreate( vUART0Task,
_STR "UART0",
mainBASIC_UART0_STACK_SIZE,
( void * ) NULL,
tskIDLE_PRIORITY,
&task_handles[TASK_UART0_MAIN]
);
if(ret != pdTRUE)
for(;;);
*/
ret = xTaskCreate( vUART1Task,
_STR "UART1",
mainBASIC_UART1_STACK_SIZE,
( void * ) NULL,
tskIDLE_PRIORITY,
&task_handles[TASK_UART1_MAIN]
);
if(ret != pdTRUE)
for(;;);
#ifdef WITH_UART2
ret = xTaskCreate( vUART2Task,
_STR "UART2",
mainBASIC_UART2_STACK_SIZE,
( void * ) NULL,
tskIDLE_PRIORITY,
&task_handles[TASK_UART2_MAIN]
);
if(ret != pdTRUE)
for(;;);
#endif
#ifdef WITH_UART3
ret = xTaskCreate( vUART3Task,
_STR "UART3",
mainBASIC_UART3_STACK_SIZE,
( void * ) NULL,
tskIDLE_PRIORITY,
&task_handles[TASK_UART3_MAIN]
);
if(ret != pdTRUE)
for(;;);
#endif
ret = xTaskCreate( vCLITask,
_STR"CLI",
mainBASIC_CLI_STACK_SIZE,
( void * ) NULL,
tskIDLE_PRIORITY,
&task_handles[TASK_CLI_MAIN] );
if(ret != pdTRUE)
for(;;);
vTaskStartScheduler();
while (1) {
// power down can go here if supported
v++;
}
return 0;
}
