// write a debug unit cpu module register
int dbg_cpu1_write_ctrl(unsigned long adr, unsigned char data) {
int err;
uint32_t dataword = data;
pthread_mutex_lock(&dbg_access_mutex);
if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
{
if ((err = adbg_select_module(DC_CPU1))) {
printf("Failed to set chain to 0x%X\n", DC_CPU1);
cable_flush();
pthread_mutex_unlock(&dbg_access_mutex);
return err;
}
if((err = adbg_ctrl_write(DBG_CPU1_REG_STATUS, &dataword, 2))) {
printf("Failed to write chain to 0x%X control reg 0x%X\n", DC_CPU1,DBG_CPU0_REG_STATUS ); // Only 2 bits: Reset, Stall
cable_flush();
pthread_mutex_unlock(&dbg_access_mutex);
return err;
}
}
else if(DEBUG_HARDWARE == DBG_HW_LEGACY)
{
if (APP_ERR_NONE == (err = legacy_dbg_set_chain(DC_CPU1)))
err = legacy_dbg_ctrl(data & 2, data & 1);
}
cable_flush();
pthread_mutex_unlock(&dbg_access_mutex);
return err;
}
/* write a debug unit cpu module register
* Since OR32 debug module has only 1 register,
* adr is ignored (for now) */
int dbg_cpu0_write_ctrl(uint32_t adr, uint8_t data) {
int err = APP_ERR_NONE;
uint32_t dataword = data;
pthread_mutex_lock(&dbg_access_mutex);
if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
{
if ((err = adbg_select_module(DC_CPU0))) {
printf("Failed to set chain to 0x%X\n", DC_CPU0);
cable_flush();
pthread_mutex_unlock(&dbg_access_mutex);
return err;
}
if((err = adbg_ctrl_write(DBG_CPU0_REG_STATUS, &dataword, 1))) { //rih: changed '2' to '1'. TODO: Should be 1 bit per NB_CORES
printf("Failed to write chain to 0x%X control reg 0x%X\n", DC_CPU0,DBG_CPU0_REG_STATUS ); // Only 2 bits: Reset, Stall
cable_flush();
pthread_mutex_unlock(&dbg_access_mutex);
return err;
}
}
else if(DEBUG_HARDWARE == DBG_HW_LEGACY)
{
if (APP_ERR_NONE == (err = legacy_dbg_set_chain(DC_CPU0)))
err = legacy_dbg_ctrl(data & 2, data &1);
}
debug("cpu0_write_ctrl(): set reg to 0x%X\n", data);
cable_flush();
pthread_mutex_unlock(&dbg_access_mutex);
return err;
}
