void ps1mb_init()
{
io_sethandler(0x0091, 0x0001, ps1_read, NULL, NULL, ps1_write, NULL, NULL, NULL);
io_sethandler(0x0092, 0x0001, ps1_read, NULL, NULL, ps1_write, NULL, NULL, NULL);
io_sethandler(0x0094, 0x0001, ps1_read, NULL, NULL, ps1_write, NULL, NULL, NULL);
io_sethandler(0x0102, 0x0004, ps1_read, NULL, NULL, ps1_write, NULL, NULL, NULL);
io_sethandler(0x0190, 0x0001, ps1_read, NULL, NULL, ps1_write, NULL, NULL, NULL);
io_sethandler(0x0320, 0x0001, ps1_read, NULL, NULL, ps1_write, NULL, NULL, NULL);
io_sethandler(0x0322, 0x0001, ps1_read, NULL, NULL, ps1_write, NULL, NULL, NULL);
io_sethandler(0x0324, 0x0001, ps1_read, NULL, NULL, ps1_write, NULL, NULL, NULL);
rom_init(&ps1_high_rom,
"roms/ibmps1es/f80000.bin",
0xf80000,
0x80000,
0x7ffff,
0,
MEM_MAPPING_EXTERNAL);
/* rom_init_interleaved(&ps1_high_rom,
"roms/ibmps1es/ibm_1057757_24-05-90.bin",
"roms/ibmps1es/ibm_1057757_29-15-90.bin",
0xfc0000,
0x40000,
0x3ffff,
0,
MEM_MAPPING_EXTERNAL);*/
ps1_190 = 0;
lpt1_remove();
lpt2_remove();
lpt1_init(0x3bc);
serial1_remove();
serial2_remove();
memset(&ps1_hd, 0, sizeof(ps1_hd));
}
void sis85c471_init()
{
int i = 0;
#ifndef RELEASE_BUILD
pclog("SiS 85c471 Init\n");
#endif
// ide_sec_disable();
lpt2_remove();
sis85c471_curreg = 0;
for (i = 0; i < 0x27; i++)
{
sis85c471_regs[i] = 0;
}
sis85c471_regs[9] = 0x40;
switch (mem_size)
{
case 0:
case 1:
sis85c471_regs[9] |= 0;
break;
case 2:
case 3:
sis85c471_regs[9] |= 1;
break;
case 4:
sis85c471_regs[9] |= 2;
break;
case 5:
sis85c471_regs[9] |= 0x20;
break;
case 6:
case 7:
sis85c471_regs[9] |= 9;
break;
case 8:
case 9:
sis85c471_regs[9] |= 4;
break;
case 10:
case 11:
sis85c471_regs[9] |= 5;
break;
case 12:
case 13:
case 14:
case 15:
sis85c471_regs[9] |= 0xB;
break;
case 16:
sis85c471_regs[9] |= 0x13;
break;
case 17:
sis85c471_regs[9] |= 0x21;
break;
case 18:
case 19:
sis85c471_regs[9] |= 6;
break;
case 20:
case 21:
case 22:
case 23:
sis85c471_regs[9] |= 0xD;
break;
case 24:
case 25:
case 26:
case 27:
case 28:
case 29:
case 30:
case 31:
sis85c471_regs[9] |= 0xE;
break;
case 32:
case 33:
case 34:
case 35:
sis85c471_regs[9] |= 0x1B;
break;
case 36:
case 37:
case 38:
case 39:
sis85c471_regs[9] |= 0xF;
break;
case 40:
case 41:
case 42:
case 43:
case 44:
case 45:
case 46:
case 47:
sis85c471_regs[9] |= 0x17;
break;
case 48:
sis85c471_regs[9] |= 0x1E;
break;
default:
if (mem_size < 64)
{
sis85c471_regs[9] |= 0x1E;
}
else if ((mem_size >= 65) && (mem_size < 68))
{
sis85c471_regs[9] |= 0x22;
}
else
{
sis85c471_regs[9] |= 0x24;
}
break;
}
sis85c471_regs[0x11] = 9;
sis85c471_regs[0x12] = 0xFF;
sis85c471_regs[0x23] = 0xF0;
sis85c471_regs[0x26] = 1;
fdc_update_densel_polarity(1);
fdc_update_densel_force(0);
fdd_swap = 0;
io_sethandler(0x0022, 0x0002, sis85c471_read, NULL, NULL, sis85c471_write, NULL, NULL, NULL);
}
static void *
sis_85c471_init(const device_t *info)
{
int mem_size_mb, i = 0;
sis_85c471_t *dev = (sis_85c471_t *) malloc(sizeof(sis_85c471_t));
memset(dev, 0, sizeof(sis_85c471_t));
lpt2_remove();
dev->cur_reg = 0;
for (i = 0; i < 0x27; i++)
dev->regs[i] = 0x00;
dev->regs[9] = 0x40;
mem_size_mb = mem_size >> 10;
switch (mem_size_mb) {
case 0: case 1:
dev->regs[9] |= 0;
break;
case 2: case 3:
dev->regs[9] |= 1;
break;
case 4:
dev->regs[9] |= 2;
break;
case 5:
dev->regs[9] |= 0x20;
break;
case 6: case 7:
dev->regs[9] |= 9;
break;
case 8: case 9:
dev->regs[9] |= 4;
break;
case 10: case 11:
dev->regs[9] |= 5;
break;
case 12: case 13: case 14: case 15:
dev->regs[9] |= 0xB;
break;
case 16:
dev->regs[9] |= 0x13;
break;
case 17:
dev->regs[9] |= 0x21;
break;
case 18: case 19:
dev->regs[9] |= 6;
break;
case 20: case 21: case 22: case 23:
dev->regs[9] |= 0xD;
break;
case 24: case 25: case 26: case 27:
case 28: case 29: case 30: case 31:
dev->regs[9] |= 0xE;
break;
case 32: case 33: case 34: case 35:
dev->regs[9] |= 0x1B;
break;
case 36: case 37: case 38: case 39:
dev->regs[9] |= 0xF;
break;
case 40: case 41: case 42: case 43:
case 44: case 45: case 46: case 47:
dev->regs[9] |= 0x17;
break;
case 48:
dev->regs[9] |= 0x1E;
break;
default:
if (mem_size_mb < 64)
dev->regs[9] |= 0x1E;
else if ((mem_size_mb >= 65) && (mem_size_mb < 68))
dev->regs[9] |= 0x22;
else
dev->regs[9] |= 0x24;
break;
}
dev->regs[0x11] = 9;
dev->regs[0x12] = 0xFF;
dev->regs[0x23] = 0xF0;
dev->regs[0x26] = 1;
dev->uart[0] = device_add_inst(&i8250_device, 1);
dev->uart[1] = device_add_inst(&i8250_device, 2);
io_sethandler(0x0022, 0x0002,
sis_85c471_read, NULL, NULL, sis_85c471_write, NULL, NULL, dev);
return dev;
}
