static void ltq_wdt_disable(void) { /* write the first password magic */ ltq_w32(LTQ_WDT_PW1, ltq_wdt_membase + LTQ_WDT_CR); /* write the second password magic with no config * this turns the watchdog off */ ltq_w32(LTQ_WDT_PW2, ltq_wdt_membase + LTQ_WDT_CR); }
void prom_putchar(char c) { unsigned long flags; local_irq_save(flags); do { } while ((ltq_r32(LTQ_ASC_FSTAT) & TXMASK) >> TXOFFSET); if (c == '\n') ltq_w32('\r', LTQ_ASC_TBUF); ltq_w32(c, LTQ_ASC_TBUF); local_irq_restore(flags); }
static void ltq_wdt_enable(void) { unsigned long int timeout = ltq_wdt_timeout * (ltq_io_region_clk_rate / LTQ_WDT_DIVIDER) + 0x1000; if (timeout > LTQ_MAX_TIMEOUT) timeout = LTQ_MAX_TIMEOUT; /* write the first password magic */ ltq_w32(LTQ_WDT_PW1, ltq_wdt_membase + LTQ_WDT_CR); /* write the second magic plus the configuration and new timeout */ ltq_w32(LTQ_WDT_SR_EN | LTQ_WDT_SR_PWD | LTQ_WDT_SR_CLKDIV | LTQ_WDT_PW2 | timeout, ltq_wdt_membase + LTQ_WDT_CR); }
int xway_nand_probe(struct platform_device *pdev) { // ltq_gpio_request(PIN_CS1, 1, 0, 1, "NAND_CS1"); ltq_gpio_request(PIN_CLE, 1, 0, 1, "NAND_CLE"); ltq_gpio_request(PIN_ALE, 1, 0, 1, "NAND_ALE"); if (ltq_is_ar9() || ltq_is_vr9()) { ltq_gpio_request(PIN_RDY, 1, 0, 0, "NAND_BSY"); ltq_gpio_request(PIN_RD, 1, 0, 1, "NAND_RD"); } ltq_ebu_w32((NAND_BASE_ADDRESS & 0x1fffff00) | ADDSEL1_MASK(3) | ADDSEL1_REGEN, LTQ_EBU_ADDSEL1); ltq_ebu_w32(BUSCON1_SETUP | BUSCON1_BCGEN_RES | BUSCON1_WAITWRC2 | BUSCON1_WAITRDC2 | BUSCON1_HOLDC1 | BUSCON1_RECOVC1 | BUSCON1_CMULT4, LTQ_EBU_BUSCON1); ltq_ebu_w32(NAND_CON_NANDM | NAND_CON_CSMUX | NAND_CON_CS_P | NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P | NAND_CON_IN_CS0 | NAND_CON_OUT_CS0, LTQ_EBU_NAND_CON); ltq_w32(NAND_WRITE_CMD_RESET, ((u32*)(NAND_BASE_ADDRESS | NAND_WRITE_CMD))); while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0); return 0; }
static int ltq_pci_config_access(unsigned char access_type, struct pci_bus *bus, unsigned int devfn, unsigned int where, u32 *data) { unsigned long cfg_base; unsigned long flags; u32 temp; /* we support slot from 0 to 15 dev_fn & 0x68 (AD29) is the SoC itself */ if ((bus->number != 0) || ((devfn & 0xf8) > 0x78) || ((devfn & 0xf8) == 0) || ((devfn & 0xf8) == 0x68)) return 1; spin_lock_irqsave(&ebu_lock, flags); cfg_base = (unsigned long) ltq_pci_mapped_cfg; cfg_base |= (bus->number << LTQ_PCI_CFG_BUSNUM_SHF) | (devfn << LTQ_PCI_CFG_FUNNUM_SHF) | (where & ~0x3); /* Perform access */ if (access_type == PCI_ACCESS_WRITE) { ltq_w32(swab32(*data), ((u32 *)cfg_base)); } else { *data = ltq_r32(((u32 *)(cfg_base))); *data = swab32(*data); } wmb(); /* clean possible Master abort */ cfg_base = (unsigned long) ltq_pci_mapped_cfg; cfg_base |= (0x0 << LTQ_PCI_CFG_FUNNUM_SHF) + 4; temp = ltq_r32(((u32 *)(cfg_base))); temp = swab32(temp); cfg_base = (unsigned long) ltq_pci_mapped_cfg; cfg_base |= (0x68 << LTQ_PCI_CFG_FUNNUM_SHF) + 4; ltq_w32(temp, ((u32 *)cfg_base)); spin_unlock_irqrestore(&ebu_lock, flags); if (((*data) == 0xffffffff) && (access_type == PCI_ACCESS_READ)) return 1; return 0; }
static void xway_select_chip(struct mtd_info *mtd, int chip) { switch (chip) { case -1: ltq_ebu_w32_mask(NAND_CON_CE, 0, LTQ_EBU_NAND_CON); ltq_ebu_w32_mask(NAND_CON_NANDM, 0, LTQ_EBU_NAND_CON); break; case 0: ltq_ebu_w32_mask(0, NAND_CON_NANDM, LTQ_EBU_NAND_CON); ltq_ebu_w32_mask(0, NAND_CON_CE, LTQ_EBU_NAND_CON); /* reset the nand chip */ while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0); ltq_w32(NAND_WRITE_CMD_RESET, ((u32*)(NAND_BASE_ADDRESS | NAND_WRITE_CMD))); break; default: BUG(); } }
void nand_write(unsigned int addr, unsigned int val) { ltq_w32(val, ((u32*)(NAND_BASE_ADDRESS | addr))); while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0); }
static inline void dbg_ltq_writel(void *a, unsigned int b) { ltq_w32(b, a); }