static bool _try_l2addr_reconfiguration(gnrc_netif_t *netif)
{
uint8_t hwaddr[GNRC_NETIF_L2ADDR_MAXLEN];
uint16_t hwaddr_len;
if (gnrc_netapi_get(netif->pid, NETOPT_SRC_LEN, 0, &hwaddr_len,
sizeof(hwaddr_len)) < 0) {
return false;
}
luid_get(hwaddr, hwaddr_len);
#if GNRC_IPV6_NIB_CONF_6LN
if (hwaddr_len == IEEE802154_LONG_ADDRESS_LEN) {
if (gnrc_netapi_set(netif->pid, NETOPT_ADDRESS_LONG, 0, hwaddr,
hwaddr_len) < 0) {
return false;
}
}
else
#endif
if (gnrc_netapi_set(netif->pid, NETOPT_ADDRESS, 0, hwaddr,
hwaddr_len) < 0) {
return false;
}
return true;
}
void mrf24j40_reset(mrf24j40_t *dev)
{
eui64_t addr_long;
mrf24j40_init(dev);
netdev_ieee802154_reset(&dev->netdev);
/* get an 8-byte unique ID to use as hardware address */
luid_get(addr_long.uint8, IEEE802154_LONG_ADDRESS_LEN);
addr_long.uint8[0] &= ~(0x01);
addr_long.uint8[0] |= (0x02);
/* set short and long address */
mrf24j40_set_addr_long(dev, ntohll(addr_long.uint64.u64));
mrf24j40_set_addr_short(dev, ntohs(addr_long.uint16[0].u16));
/* set default PAN id */
mrf24j40_set_pan(dev, IEEE802154_DEFAULT_PANID);
mrf24j40_set_chan(dev, IEEE802154_DEFAULT_CHANNEL);
/* configure Immediate Sleep and Wake-Up mode */
mrf24j40_reg_write_short(dev, MRF24J40_REG_WAKECON, MRF24J40_WAKECON_IMMWAKE);
/* set default options */
mrf24j40_set_option(dev, IEEE802154_FCF_PAN_COMP, true);
mrf24j40_set_option(dev, NETDEV_IEEE802154_SRC_MODE_LONG, true);
mrf24j40_set_option(dev, NETDEV_IEEE802154_ACK_REQ, true);
mrf24j40_set_option(dev, MRF24J40_OPT_CSMA, true);
/* go into RX state */
mrf24j40_reset_tasks(dev);
dev->state = 0;
mrf24j40_set_state(dev, MRF24J40_PSEUDO_STATE_IDLE);
DEBUG("mrf24j40_reset(): reset complete.\n");
}
static void kw2xrf_set_address(kw2xrf_t *dev)
{
DEBUG("[kw2xrf] set MAC addresses\n");
eui64_t addr_long;
/* get an 8-byte unique ID to use as hardware address */
luid_get(addr_long.uint8, IEEE802154_LONG_ADDRESS_LEN);
/* make sure we mark the address as non-multicast and not globally unique */
addr_long.uint8[0] &= ~(0x01);
addr_long.uint8[0] |= (0x02);
/* set short and long address */
kw2xrf_set_addr_long(dev, ntohll(addr_long.uint64.u64));
kw2xrf_set_addr_short(dev, ntohs(addr_long.uint16[0].u16));
}
void encode_init(void)
{
uint8_t tmp[5];
luid_get(tmp, 5);
/* extract device ID */
hex_str(tmp, 5, did);
// /* and 'pseudo-randomize' the device ID to get sensor IDs */
// for (int i = 0; i < 3; i++) {
// for (int p = 0; p < 5; p++) {
// tmp[p] ^= rand[i];
// }
// hex_str(tmp, 5, sid[i]);
// }
}
void cord_common_init(void)
{
#ifdef CORD_EP
memcpy(cord_common_ep, CORD_EP, BUFSIZE);
#else
uint8_t luid[CORD_EP_SUFFIX_LEN / 2];
if (PREFIX_LEN > 1) {
memcpy(cord_common_ep, CORD_EP_PREFIX, (PREFIX_LEN - 1));
}
luid_get(luid, sizeof(luid));
fmt_bytes_hex(&cord_common_ep[PREFIX_LEN - 1], luid, sizeof(luid));
cord_common_ep[BUFSIZE - 1] = '\0';
#endif
}
void at86rf2xx_reset(at86rf2xx_t *dev)
{
eui64_t addr_long;
at86rf2xx_hardware_reset(dev);
/* Reset state machine to ensure a known state */
at86rf2xx_reset_state_machine(dev);
/* reset options and sequence number */
dev->netdev.seq = 0;
dev->netdev.flags = 0;
/* get an 8-byte unique ID to use as hardware address */
luid_get(addr_long.uint8, IEEE802154_LONG_ADDRESS_LEN);
/* make sure we mark the address as non-multicast and not globally unique */
addr_long.uint8[0] &= ~(0x01);
addr_long.uint8[0] |= (0x02);
/* set short and long address */
at86rf2xx_set_addr_long(dev, NTOHLL(addr_long.uint64.u64));
at86rf2xx_set_addr_short(dev, NTOHS(addr_long.uint16[0].u16));
/* set default PAN id */
at86rf2xx_set_pan(dev, AT86RF2XX_DEFAULT_PANID);
/* set default channel */
at86rf2xx_set_chan(dev, AT86RF2XX_DEFAULT_CHANNEL);
/* set default TX power */
at86rf2xx_set_txpower(dev, AT86RF2XX_DEFAULT_TXPOWER);
/* set default options */
at86rf2xx_set_option(dev, AT86RF2XX_OPT_AUTOACK, true);
at86rf2xx_set_option(dev, AT86RF2XX_OPT_CSMA, true);
at86rf2xx_set_option(dev, AT86RF2XX_OPT_TELL_RX_START, false);
at86rf2xx_set_option(dev, AT86RF2XX_OPT_TELL_RX_END, true);
#ifdef MODULE_NETSTATS_L2
at86rf2xx_set_option(dev, AT86RF2XX_OPT_TELL_TX_END, true);
#endif
/* set default protocol */
#ifdef MODULE_GNRC_SIXLOWPAN
dev->netdev.proto = GNRC_NETTYPE_SIXLOWPAN;
#elif MODULE_GNRC
dev->netdev.proto = GNRC_NETTYPE_UNDEF;
#endif
/* enable safe mode (protect RX FIFO until reading data starts) */
at86rf2xx_reg_write(dev, AT86RF2XX_REG__TRX_CTRL_2,
AT86RF2XX_TRX_CTRL_2_MASK__RX_SAFE_MODE);
#ifdef MODULE_AT86RF212B
at86rf2xx_set_page(dev, 0);
#endif
/* don't populate masked interrupt flags to IRQ_STATUS register */
uint8_t tmp = at86rf2xx_reg_read(dev, AT86RF2XX_REG__TRX_CTRL_1);
tmp &= ~(AT86RF2XX_TRX_CTRL_1_MASK__IRQ_MASK_MODE);
at86rf2xx_reg_write(dev, AT86RF2XX_REG__TRX_CTRL_1, tmp);
/* disable clock output to save power */
tmp = at86rf2xx_reg_read(dev, AT86RF2XX_REG__TRX_CTRL_0);
tmp &= ~(AT86RF2XX_TRX_CTRL_0_MASK__CLKM_CTRL);
tmp &= ~(AT86RF2XX_TRX_CTRL_0_MASK__CLKM_SHA_SEL);
tmp |= (AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__OFF);
at86rf2xx_reg_write(dev, AT86RF2XX_REG__TRX_CTRL_0, tmp);
/* enable interrupts */
at86rf2xx_reg_write(dev, AT86RF2XX_REG__IRQ_MASK,
AT86RF2XX_IRQ_STATUS_MASK__TRX_END);
/* clear interrupt flags */
at86rf2xx_reg_read(dev, AT86RF2XX_REG__IRQ_STATUS);
/* go into RX state */
at86rf2xx_set_state(dev, AT86RF2XX_STATE_RX_AACK_ON);
DEBUG("at86rf2xx_reset(): reset complete.\n");
}
int cc2420_init(cc2420_t *dev)
{
uint16_t reg;
uint8_t addr[8];
/* reset options and sequence number */
dev->netdev.seq = 0;
dev->netdev.flags = 0;
/* set default address, channel, PAN ID, and TX power */
luid_get(addr, sizeof(addr));
/* make sure we mark the address as non-multicast and not globally unique */
addr[0] &= ~(0x01);
addr[0] |= 0x02;
cc2420_set_addr_short(dev, &addr[6]);
cc2420_set_addr_long(dev, addr);
cc2420_set_pan(dev, CC2420_PANID_DEFAULT);
cc2420_set_chan(dev, CC2420_CHAN_DEFAULT);
cc2420_set_txpower(dev, CC2420_TXPOWER_DEFAULT);
/* set default options */
cc2420_set_option(dev, CC2420_OPT_AUTOACK, true);
cc2420_set_option(dev, CC2420_OPT_CSMA, true);
cc2420_set_option(dev, CC2420_OPT_TELL_TX_START, true);
cc2420_set_option(dev, CC2420_OPT_TELL_RX_END, true);
#ifdef MODULE_NETSTATS_L2
cc2420_set_option(dev, CC2420_OPT_TELL_RX_END, true);
#endif
/* set default protocol*/
#ifdef MODULE_GNRC_SIXLOWPAN
dev->netdev.proto = GNRC_NETTYPE_SIXLOWPAN;
#elif MODULE_GNRC
dev->netdev.proto = GNRC_NETTYPE_UNDEF;
#endif
/* change default RX bandpass filter to 1.3uA (as recommended) */
reg = cc2420_reg_read(dev, CC2420_REG_RXCTRL1);
reg |= CC2420_RXCTRL1_RXBPF_LOCUR;
cc2420_reg_write(dev, CC2420_REG_RXCTRL1, reg);
/* set the FIFOP threshold to maximum. */
cc2420_reg_write(dev, CC2420_REG_IOCFG0, CC2420_PKT_MAXLEN);
/* turn off "Security enable" (page 33). */
reg = cc2420_reg_read(dev, CC2420_REG_SECCTRL0);
reg &= ~CC2420_SECCTRL0_RXFIFO_PROT;
cc2420_reg_write(dev, CC2420_REG_SECCTRL0, reg);
/* set preamble length to 3 leading zero byte */
/* and turn on hardware CRC generation */
reg = cc2420_reg_read(dev, CC2420_REG_MDMCTRL0);
reg &= ~(CC2420_MDMCTRL0_PREAMBLE_M);
reg |= CC2420_MDMCTRL0_PREAMBLE_3B;
reg |= CC2420_MDMCTRL0_AUTOCRC;
cc2420_reg_write(dev, CC2420_REG_MDMCTRL0, reg);
/* go into RX state */
cc2420_set_state(dev, CC2420_GOTO_RX);
return 0;
}