u32 lx_plx_mbox_read(struct lx6464es *chip, int mbox_nr)
{
int index;
switch (mbox_nr) {
case 1:
index = ePLX_MBOX1; break;
case 2:
index = ePLX_MBOX2; break;
case 3:
index = ePLX_MBOX3; break;
case 4:
index = ePLX_MBOX4; break;
case 5:
index = ePLX_MBOX5; break;
case 6:
index = ePLX_MBOX6; break;
case 7:
index = ePLX_MBOX7; break;
case 0: /* reserved for HF flags */
snd_BUG();
default:
return 0xdeadbeef;
}
return lx_plx_reg_read(chip, index);
}
/* reset the dsp during initialization */
static int lx_init_xilinx_reset(struct lx6464es *chip)
{
int i;
u32 plx_reg = lx_plx_reg_read(chip, ePLX_CHIPSC);
dev_dbg(chip->card->dev, "->lx_init_xilinx_reset\n");
/* activate reset of xilinx */
plx_reg &= ~CHIPSC_RESET_XILINX;
lx_plx_reg_write(chip, ePLX_CHIPSC, plx_reg);
msleep(1);
lx_plx_reg_write(chip, ePLX_MBOX3, 0);
msleep(1);
plx_reg |= CHIPSC_RESET_XILINX;
lx_plx_reg_write(chip, ePLX_CHIPSC, plx_reg);
/* deactivate reset of xilinx */
for (i = 0; i != 100; ++i) {
u32 reg_mbox3;
msleep(10);
reg_mbox3 = lx_plx_reg_read(chip, ePLX_MBOX3);
if (reg_mbox3) {
dev_dbg(chip->card->dev, "xilinx reset done\n");
dev_dbg(chip->card->dev, "xilinx took %d loops\n", i);
break;
}
}
/* todo: add some error handling? */
/* clear mr */
lx_dsp_reg_write(chip, eReg_CSM, 0);
/* le xilinx ES peut ne pas etre encore pret, on attend. */
msleep(600);
return 0;
}