// add a 6809 cpu
void m1snd_add6809(long clock, void *handlers)
{
char *ctx;
int cpunum;
rw6809 = handlers;
ctx = malloc(4*1024);
cpunum = timer_add_cpu(CPU_M6809, clock, m6809_execute, m6809_getcycles, m6809_yield, m6809_getctx, m6809_setctx, ctx);
// printf("Adding 6809 CPU #%d, ctx=%x\n", cpunum, (unsigned int)ctx);
m6809_reset(NULL);
m6809_set_irq_callback(m6809_irq_callback);
m6809_getctx(ctx);
}
// 6809, managed via memory manager
void m1snd_add6809b(long clock, void *handlers)
{
char *ctx;
int cpunum;
rw6809 = &m6809b;
ctx = malloc(4*1024);
cpunum = timer_add_cpu(CPU_M6809, clock, m6809_execute, m6809_getcycles, m6809_yield, m6809_getctx, m6809_setctx, ctx);
// printf("Adding 6809b CPU #%d, ctx=%x\n", cpunum, (unsigned int)ctx);
memory_register_cpu(cpunum, 8, M1_CPU_LE);
memory_context_switch(cpunum);
m6809_reset(NULL);
m6809_set_irq_callback(m6809_irq_callback);
m6809_getctx(ctx);
}
void cpu_run(void)
{
int totalcpu,usres;
unsigned char *ROM0; /* opcode decryption is currently supported only for the first memory region */
ROM0 = ROM;
/* count how many CPUs we have to emulate */
totalcpu = 0;
while (totalcpu < MAX_CPU)
{
const struct MemoryReadAddress *mra;
const struct MemoryWriteAddress *mwa;
if (Machine->drv->cpu[totalcpu].cpu_type == 0) break;
/* if sound is disabled, don't emulate the audio CPU */
if (play_sound == 0 && (Machine->drv->cpu[totalcpu].cpu_type & CPU_AUDIO_CPU))
cpurunning[totalcpu] = 0;
else
cpurunning[totalcpu] = 1;
/* initialize the memory base pointers for memory hooks */
RAM = Machine->memory_region[Machine->drv->cpu[totalcpu].memory_region];
mra = Machine->drv->cpu[totalcpu].memory_read;
while (mra->start != -1)
{
if (mra->base) *mra->base = &RAM[mra->start];
mra++;
}
mwa = Machine->drv->cpu[totalcpu].memory_write;
while (mwa->start != -1)
{
if (mwa->base) *mwa->base = &RAM[mwa->start];
mwa++;
}
totalcpu++;
}
#ifdef BUGS
extern void g_exec(void);
g_exec();
#else // BUGS
reset:
for (activecpu = 0; activecpu < totalcpu; activecpu++)
{
int cycles;
cycles = Machine->drv->cpu[activecpu].cpu_clock /
(Machine->drv->frames_per_second * Machine->drv->cpu[activecpu].interrupts_per_frame);
switch(Machine->drv->cpu[activecpu].cpu_type & ~CPU_FLAGS_MASK)
{
case CPU_Z80:
{
struct z80context *ctxt;
ctxt = (struct z80context *)cpucontext[activecpu];
Z80_Reset();
Z80_GetRegs(&ctxt->regs);
ctxt->icount = cycles;
ctxt->iperiod = cycles;
ctxt->irq = Z80_IGNORE_INT;
}
break;
#if 0
case CPU_M6502:
{
M6502 *ctxt;
ctxt = (M6502 *)cpucontext[activecpu];
/* Reset6502() needs to read memory to get the PC start address */
RAM = Machine->memory_region[Machine->drv->cpu[activecpu].memory_region];
memoryread = Machine->drv->cpu[activecpu].memory_read;
ctxt->IPeriod = cycles; /* must be done before Reset6502() */
Reset6502(ctxt);
}
break;
case CPU_I86:
RAM = Machine->memory_region[Machine->drv->cpu[activecpu].memory_region];
I86_Reset(RAM,cycles);
break;
/* DS... */
case CPU_M6809:
{
struct m6809context *ctxt;
ctxt = (struct m6809context *)cpucontext[activecpu];
/* m6809_reset() needs to read memory to get the PC start address */
RAM = Machine->memory_region[Machine->drv->cpu[activecpu].memory_region];
memoryread = Machine->drv->cpu[activecpu].memory_read;
m6809_IPeriod = cycles;
m6809_reset();
m6809_GetRegs(&ctxt->regs);
ctxt->icount = cycles;
ctxt->iperiod = cycles;
ctxt->irq = INT_NONE;
}
break;
#endif
/* ...DS */
}
}
do
{
for (activecpu = 0; activecpu < totalcpu; activecpu++)
{
if (cpurunning[activecpu])
{
int loops;
memoryread = Machine->drv->cpu[activecpu].memory_read;
memorywrite = Machine->drv->cpu[activecpu].memory_write;
RAM = Machine->memory_region[Machine->drv->cpu[activecpu].memory_region];
/* opcode decryption is currently supported only for the first memory region */
if (activecpu == 0) ROM = ROM0;
else ROM = RAM;
switch(Machine->drv->cpu[activecpu].cpu_type & ~CPU_FLAGS_MASK)
{
case CPU_Z80:
{
struct z80context *ctxt;
ctxt = (struct z80context *)cpucontext[activecpu];
Z80_SetRegs(&ctxt->regs);
Z80_ICount = ctxt->icount;
Z80_IPeriod = ctxt->iperiod;
Z80_IRQ = ctxt->irq;
for (loops = 0; loops < Machine->drv->cpu[activecpu].interrupts_per_frame; loops++)
Z80_Execute();
Z80_GetRegs(&ctxt->regs);
ctxt->icount = Z80_ICount;
ctxt->iperiod = Z80_IPeriod;
ctxt->irq = Z80_IRQ;
}
break;
#if 0
case CPU_M6502:
for (loops = 0; loops < Machine->drv->cpu[activecpu].interrupts_per_frame; loops++)
Run6502((M6502 *)cpucontext[activecpu]);
break;
case CPU_I86:
for (loops = 0; loops < Machine->drv->cpu[activecpu].interrupts_per_frame; loops++)
I86_Execute();
break;
/* DS... */
case CPU_M6809:
{
struct m6809context *ctxt;
ctxt = (struct m6809context *)cpucontext[activecpu];
m6809_SetRegs(&ctxt->regs);
m6809_ICount = ctxt->icount;
m6809_IPeriod = ctxt->iperiod;
m6809_IRequest = ctxt->irq;
for (loops = 0; loops < Machine->drv->cpu[activecpu].interrupts_per_frame; loops++)
m6809_execute();
m6809_GetRegs(&ctxt->regs);
ctxt->icount = m6809_ICount;
ctxt->iperiod = m6809_IPeriod;
ctxt->irq = m6809_IRequest;
}
break;
#endif
/* ...DS */
}
}
}
usres = updatescreen();
if (usres == 2) /* user asked to reset the machine */
goto reset;
} while (usres == 0);
#endif // BUGS
}
