void aica_device::CheckPendingIRQ()
{
UINT32 pend=m_udata.data[0xa0/2];
UINT32 en=m_udata.data[0x9c/2];
if(m_MidiW!=m_MidiR)
{
m_IRQL = m_IrqMidi;
m_irq_cb(1);
return;
}
if(!pend)
return;
if(pend&0x40)
if(en&0x40)
{
m_IRQL = m_IrqTimA;
m_irq_cb(1);
return;
}
if(pend&0x80)
if(en&0x80)
{
m_IRQL = m_IrqTimBC;
m_irq_cb(1);
return;
}
if(pend&0x100)
if(en&0x100)
{
m_IRQL = m_IrqTimBC;
m_irq_cb(1);
return;
}
}
void wd33c9x_base_device::update_irq()
{
if (m_regs[AUXILIARY_STATUS] & AUXILIARY_STATUS_INT) {
m_regs[AUXILIARY_STATUS] &= ~AUXILIARY_STATUS_INT;
LOGMASKED(LOG_LINES, "%s: Clearing IRQ\n", shortname());
m_irq_cb(CLEAR_LINE);
}
if (!irq_fifo_empty()) {
m_regs[SCSI_STATUS] = irq_fifo_pop();
m_regs[AUXILIARY_STATUS] |= AUXILIARY_STATUS_INT;
const uint8_t cc = (m_regs[COMMAND] & COMMAND_CC);
if (cc == COMMAND_CC_SELECT_TRANSFER || cc == COMMAND_CC_SELECT_ATN_TRANSFER) {
switch (m_regs[SCSI_STATUS]) {
case SCSI_STATUS_DISCONNECT:
if (!(m_regs[CONTROL] & CONTROL_IDI)) {
return;
}
break;
case SCSI_STATUS_SELECT_TRANSFER_SUCCESS:
if ((m_regs[CONTROL] & CONTROL_EDI) && m_mode != MODE_D) {
return;
}
break;
}
}
LOGMASKED(LOG_LINES, "%s: Asserting IRQ - SCSI Status (%02x)\n", shortname(), m_regs[SCSI_STATUS]);
m_irq_cb(ASSERT_LINE);
}
}
void aica_device::ResetInterrupts()
{
#if 0
UINT32 reset = m_udata.data[0xa4/2];
if (reset & 0x40)
m_irq_cb(-m_IrqTimA);
if (reset & 0x180)
m_irq_cb(-m_IrqTimBC);
#endif
}
void mos6530_base_t::update_irq()
{
int state = CLEAR_LINE;
if (m_ie_timer && m_irq_timer) state = ASSERT_LINE;
if (m_ie_edge && m_irq_edge) state = ASSERT_LINE;
m_irq_cb(state);
}
void riot6532_device::update_irqstate()
{
int irq = (m_irqstate & m_irqenable) ? ASSERT_LINE : CLEAR_LINE;
if (m_irq != irq)
{
m_irq_cb(irq);
m_irq = irq;
}
}
void scsp_device::ResetInterrupts()
{
UINT32 reset = m_udata.data[0x22/2];
if (reset & 0x40)
{
m_irq_cb(m_IrqTimA, CLEAR_LINE);
}
if (reset & 0x180)
{
m_irq_cb(m_IrqTimBC, CLEAR_LINE);
}
if (reset & 0x8)
{
m_irq_cb(m_IrqMidi, CLEAR_LINE);
}
CheckPendingIRQ();
}
void dp8390_device::device_reset() {
memset(&m_regs, 0, sizeof(m_regs));
m_regs.cr = 0x21;
m_regs.isr = 0x80;
m_regs.dcr = 0x04;
memset(&m_8019regs, 0, sizeof(m_8019regs));
m_8019regs.config1 = 0x80;
m_8019regs.config3 = 0x01;
m_irq_cb(CLEAR_LINE);
m_reset = 1;
}
void scsp_device::CheckPendingIRQ()
{
UINT32 pend=m_udata.data[0x20/2];
UINT32 en=m_udata.data[0x1e/2];
if(m_MidiW!=m_MidiR)
{
m_udata.data[0x20/2] |= 8;
pend |= 8;
}
if(!pend)
return;
if(pend&0x40)
if(en&0x40)
{
m_irq_cb(m_IrqTimA, ASSERT_LINE);
return;
}
if(pend&0x80)
if(en&0x80)
{
m_irq_cb(m_IrqTimBC, ASSERT_LINE);
return;
}
if(pend&0x100)
if(en&0x100)
{
m_irq_cb(m_IrqTimBC, ASSERT_LINE);
return;
}
if(pend&8)
if (en&8)
{
m_irq_cb(m_IrqMidi, ASSERT_LINE);
m_udata.data[0x20/2] &= ~8;
return;
}
m_irq_cb((offs_t)0, CLEAR_LINE);
}
void lsi53c810_device::dmaop_interrupt()
{
if(dcmd & 0x100000) {
fatalerror("LSI53C810: INTFLY opcode not implemented\n");
}
dsps = FETCH();
istat |= 0x1; /* DMA interrupt pending */
dstat |= 0x4; /* SIR (SCRIPTS Interrupt Instruction Received) */
if (!m_irq_cb.isnull())
m_irq_cb(1);
dma_icount = 0;
halted = 1;
}
void wd33c9x_base_device::device_reset()
{
scsi_bus->ctrl_w(scsi_refid, 0, S_ALL);
scsi_bus->ctrl_wait(scsi_refid, S_SEL|S_BSY|S_RST, S_ALL);
m_addr = 0;
for (uint8_t reg = 0; reg < NUM_REGS; ++reg) {
// FIXME - QUEUE_TAG is a valid register for 93B only
m_regs[reg] = (QUEUE_TAG <= reg && reg <= INVALID_1E) ? 0xff : 0;
}
m_command_length = 0;
set_scsi_state(IDLE);
m_mode = MODE_D;
m_xfr_phase = 0;
m_step_count = 0;
m_transfer_count = 0;
data_fifo_reset();
irq_fifo_reset();
m_irq_cb(CLEAR_LINE);
m_drq_cb(CLEAR_LINE);
m_drq_state = false;
}
void dp8390_device::stop() {
m_regs.isr = 0x80; // is this right?
m_regs.cr |= 1;
m_irq_cb(CLEAR_LINE);
m_reset = 1;
}
void svision_sound_device::sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples)
{
stream_sample_t *left=outputs[0], *right=outputs[1];
int i, j;
SVISION_CHANNEL *channel;
for (i = 0; i < samples; i++, left++, right++)
{
*left = 0;
*right = 0;
for (channel=m_channel, j=0; j<ARRAY_LENGTH(m_channel); j++, channel++)
{
if (channel->size != 0)
{
if (channel->on||channel->count)
{
int on = FALSE;
switch (channel->waveform)
{
case 0:
on = channel->pos <= (28 * channel->size) >> 5;
break;
case 1:
on = channel->pos <= (24 * channel->size) >> 5;
break;
default:
case 2:
on = channel->pos <= channel->size / 2;
break;
case 3:
on = channel->pos <= (9 * channel->size) >> 5;
break;
}
{
INT16 s = on ? channel->volume << 8 : 0;
if (j == 0)
*right += s;
else
*left += s;
}
}
channel->pos++;
if (channel->pos >= channel->size)
channel->pos = 0;
}
}
if (m_noise.on && (m_noise.play || m_noise.count))
{
INT16 s = (m_noise.value ? 1 << 8: 0) * m_noise.volume;
int b1, b2;
if (m_noise.left)
*left += s;
if (m_noise.right)
*right += s;
m_noise.pos += m_noise.step;
if (m_noise.pos >= 1.0)
{
switch (m_noise.type)
{
case SVISION_NOISE_Type7Bit:
m_noise.value = m_noise.state & 0x40 ? 1 : 0;
b1 = (m_noise.state & 0x40) != 0;
b2 = (m_noise.state & 0x20) != 0;
m_noise.state=(m_noise.state<<1)+(b1!=b2?1:0);
break;
case SVISION_NOISE_Type14Bit:
default:
m_noise.value = m_noise.state & 0x2000 ? 1 : 0;
b1 = (m_noise.state & 0x2000) != 0;
b2 = (m_noise.state & 0x1000) != 0;
m_noise.state = (m_noise.state << 1) + (b1 != b2 ? 1 : 0);
}
m_noise.pos -= 1;
}
}
if (m_dma.on)
{
UINT8 sample;
INT16 s;
UINT16 addr = m_dma.start + (unsigned) m_dma.pos / 2;
if (addr >= 0x8000 && addr < 0xc000)
{
sample = machine().root_device().memregion("user1")->base()[(addr & 0x3fff) | m_dma.ca14to16];
}
else
{
sample = machine().device("maincpu")->memory().space(AS_PROGRAM).read_byte(addr);
}
if (((unsigned)m_dma.pos) & 1)
s = (sample & 0xf);
else
s = (sample & 0xf0) >> 4;
s <<= 8;
if (m_dma.left)
*left += s;
if (m_dma.right)
*right += s;
m_dma.pos += m_dma.step;
if (m_dma.pos >= m_dma.size)
{
m_dma.finished = TRUE;
m_dma.on = FALSE;
m_irq_cb();
}
}
