void fga002_device::trigger_interrupt(uint8_t data) { uint8_t icr = 0; LOGINT(("%s(%02x)\n", FUNCNAME, data)); /* The Interrupt Control Register (ICR*) bit, must be set for the correspondning channel */ // TODO: Support programmable assert level for interrupt source switch(data) { case INT_LOCAL0: icr = m_fga002[FGA_ICRLOCAL0]; m_fga002[FGA_ISLOCAL0] = 0x00; break; case INT_LOCAL1: icr = m_fga002[FGA_ICRLOCAL1]; m_fga002[FGA_ISLOCAL1] = 0x00; break; case INT_LOCAL2: icr = m_fga002[FGA_ICRLOCAL2]; m_fga002[FGA_ISLOCAL2] = 0x00; break; case INT_LOCAL3: icr = m_fga002[FGA_ICRLOCAL3]; m_fga002[FGA_ISLOCAL3] = 0x00; break; case INT_LOCAL4: icr = m_fga002[FGA_ICRLOCAL4]; m_fga002[FGA_ISLOCAL4] = 0x00; break; case INT_LOCAL5: icr = m_fga002[FGA_ICRLOCAL5]; m_fga002[FGA_ISLOCAL5] = 0x00; break; case INT_LOCAL6: icr = m_fga002[FGA_ICRLOCAL6]; m_fga002[FGA_ISLOCAL6] = 0x00; break; case INT_LOCAL7: icr = m_fga002[FGA_ICRLOCAL7]; m_fga002[FGA_ISLOCAL7] = 0x00; break; default: LOGINT((" - interrupt source %d - not supported", data)); return; } if ((icr & REG_ICR_ENABLE) == 0 || (icr & REG_ICR_LVL_MSK) == 0) { LOGINT((" - The Interrupt Control Register bit for channel %02x is not set or level is 0, blocking attempt to interrupt\n", data)); return; } m_irq_level = icr & REG_ICR_LVL_MSK; LOGINT((" - Interrupt Level %d, caused by ICR %02x with vector %02x\n", m_irq_level, icr, data )); // trigger intrrupt to CPU through board driver callback. m_out_int_cb(ASSERT_LINE); }
/* ints will continue to be set for as long as there are ints pending */ void ins8250_uart_device::update_interrupt() { int state; /* if any bits are set and are enabled */ if (((m_int_pending & m_regs.ier) & 0x0f) != 0) { /* trigger next highest priority int */ /* set int */ state = 1; m_regs.iir &= ~(0x08|0x04|0x02); /* highest to lowest */ if (m_regs.ier & m_int_pending & COM_INT_PENDING_RECEIVER_LINE_STATUS) m_regs.iir |=0x04|0x02; else if (m_regs.ier & m_int_pending & COM_INT_PENDING_RECEIVED_DATA_AVAILABLE) { m_regs.iir |=0x04; if ((m_int_pending & COM_INT_PENDING_CHAR_TIMEOUT) == 0x11) m_regs.iir |= 0x08; } else if (m_regs.ier & m_int_pending & COM_INT_PENDING_TRANSMITTER_HOLDING_REGISTER_EMPTY) m_regs.iir |=0x02; /* int pending */ m_regs.iir &= ~0x01; } else { /* clear int */ state = 0; /* no ints pending */ m_regs.iir |= 0x01; /* priority level */ m_regs.iir &= ~(0x08|0x04|0x02); } /* set or clear the int */ m_out_int_cb(state); }
//------------------------------------------------- // check_interrupts - //------------------------------------------------- void z80sio_device::check_interrupts() { LOGINT("%s %s \n",FUNCNAME, tag()); int state = (z80daisy_irq_state() & Z80_DAISY_INT) ? ASSERT_LINE : CLEAR_LINE; m_out_int_cb(state); }
void z80dma_device::interrupt_check() { m_out_int_cb(m_ip ? ASSERT_LINE : CLEAR_LINE); }
void z80dart_device::check_interrupts() { int state = (z80daisy_irq_state() & Z80_DAISY_INT) ? ASSERT_LINE : CLEAR_LINE; m_out_int_cb(state); }