/*
* We only do anything if we are the master NPU on the board.
* The slave NPU only has the ethernet chip going directly to
* the PCIB interrupt input.
*/
void __init ixdp2x01_init_irq(void)
{
int irq = 0;
/* initialize chip specific interrupts */
ixp2000_init_irq();
if (machine_is_ixdp2401())
valid_irq_mask = IXDP2401_VALID_IRQ_MASK;
else
valid_irq_mask = IXDP2801_VALID_IRQ_MASK;
/* Mask all interrupts from CPLD, disable simulation */
ixp2000_reg_write(IXDP2X01_INT_MASK_SET_REG, 0xffffffff);
ixp2000_reg_write(IXDP2X01_INT_SIM_REG, 0);
for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) {
if (irq & valid_irq_mask) {
set_irq_chip(irq, &ixdp2x01_irq_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_flags(irq, IRQF_VALID);
} else {
set_irq_flags(irq, 0);
}
}
/* Hook into PCI interrupts */
set_irq_chained_handler(IRQ_IXP2000_PCIB, &ixdp2x01_irq_handler);
}
int __init ixdp2x01_pci_init(void)
{
if (machine_is_ixdp2401() || machine_is_ixdp2801() ||\
machine_is_ixdp28x5())
pci_common_init(&ixdp2x01_pci);
return 0;
}
static int __init ixdp2x01_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
u8 bus = dev->bus->number;
u32 devpin = DEVPIN(PCI_SLOT(dev->devfn), pin);
struct pci_bus *tmp_bus = dev->bus;
/* Primary bus, no interrupts here */
if (bus == 0) {
return -1;
}
/* Lookup first leaf in bus tree */
while ((tmp_bus->parent != NULL) && (tmp_bus->parent->parent != NULL)) {
tmp_bus = tmp_bus->parent;
}
/* Select between known bridges */
switch (tmp_bus->self->devfn | (tmp_bus->self->bus->number << 8)) {
/* Device is located after first MB bridge */
case 0x0008:
if (tmp_bus == dev->bus) {
/* Device is located directy after first MB bridge */
switch (devpin) {
case DEVPIN(1, 1): /* Onboard 82546 ch 0 */
if (machine_is_ixdp2401())
return IRQ_IXDP2401_INTA_82546;
return -1;
case DEVPIN(1, 2): /* Onboard 82546 ch 1 */
if (machine_is_ixdp2401())
return IRQ_IXDP2401_INTB_82546;
return -1;
case DEVPIN(0, 1): /* PMC INTA# */
return IRQ_IXDP2X01_SPCI_PMC_INTA;
case DEVPIN(0, 2): /* PMC INTB# */
return IRQ_IXDP2X01_SPCI_PMC_INTB;
case DEVPIN(0, 3): /* PMC INTC# */
return IRQ_IXDP2X01_SPCI_PMC_INTC;
case DEVPIN(0, 4): /* PMC INTD# */
return IRQ_IXDP2X01_SPCI_PMC_INTD;
}
}
break;
case 0x0010:
if (tmp_bus == dev->bus) {
/* Device is located directy after second MB bridge */
/* Secondary bus of second bridge */
switch (devpin) {
case DEVPIN(0, 1): /* DB#0 */
return IRQ_IXDP2X01_SPCI_DB_0;
case DEVPIN(1, 1): /* DB#1 */
return IRQ_IXDP2X01_SPCI_DB_1;
}
} else {
/* Device is located indirectly after second MB bridge */
/* Not supported now */
}
break;
}
return -1;
}
