static void otg_set_utmi_xcvr(void) { u32 tmp; struct clk *usb_clk; /* Stop then Reset */ UOG_USBCMD &= ~UCMD_RUN_STOP; while (UOG_USBCMD & UCMD_RUN_STOP) ; UOG_USBCMD |= UCMD_RESET; while ((UOG_USBCMD) & (UCMD_RESET)) ; if (cpu_is_mx51()) { /* OTG Polarity of Overcurrent is Low active */ USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_OC_POL; /* Enable OTG Overcurrent Event */ USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_OC_DIS; } else { /* USBOTG_PWR low active */ USBCTRL &= ~UCTRL_PP; /* OverCurrent Polarity is Low Active */ USBCTRL &= ~UCTRL_OCPOL; /* OTG Lock Disable */ USBCTRL |= UCTRL_OLOCKD; } USBCTRL &= ~UCTRL_OPM; /* OTG Power Mask */ /* set UTMI xcvr */ tmp = UOG_PORTSC1 & ~PORTSC_PTS_MASK; tmp |= PORTSC_PTS_UTMI; UOG_PORTSC1 = tmp; if (cpu_is_mx51()) { /* Set the PHY clock to 19.2MHz */ USB_PHY_CTR_FUNC2 &= ~USB_UTMI_PHYCTRL2_PLLDIV_MASK; USB_PHY_CTR_FUNC2 |= 0x01; } else if (machine_is_mx35_3ds()) { /* Enable UTMI interface in PHY control Reg */ USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_UTMI_ENABLE; } else if(machine_is_mx37_3ds()) { printk("before change USB_PHY_CTR_FUNC2 = 0x%x \n", USB_PHY_CTR_FUNC2); USB_PHY_CTR_FUNC2 &= ~(3<<19); USB_PHY_CTR_FUNC2 |= (0<<19); //USB_PHY_CTR_FUNC2 &= ~(3<<19); //USB_PHY_CTR_FUNC2 |= (1<<19); //USB_PHY_CTR_FUNC2 &= ~(3<<19); //USB_PHY_CTR_FUNC2 |= (2<<19); //USB_PHY_CTR_FUNC2 &= ~(3<<19); //USB_PHY_CTR_FUNC2 |= (3<<19); printk("USB_PHY_CTR_FUNC2 = 0x%x \n", USB_PHY_CTR_FUNC2); } /* need to reset the controller here so that the ID pin * is correctly detected. */ /* Stop then Reset */ UOG_USBCMD &= ~UCMD_RUN_STOP; while (UOG_USBCMD & UCMD_RUN_STOP) ; UOG_USBCMD |= UCMD_RESET; while ((UOG_USBCMD) & (UCMD_RESET)) ; /* allow controller to reset, and leave time for * the ULPI transceiver to reset too. */ msleep(100); if (cpu_is_mx37()) { usb_clk = clk_get(NULL, "usboh2_clk"); clk_disable(usb_clk); clk_put(usb_clk); /* fix USB PHY Power Gating leakage issue for i.MX37 */ USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_CHGRDETON; USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_CHGRDETEN; UOG_PORTSC1 |= PORTSC_PHCD; } }
static void otg_set_utmi_xcvr(void) { u32 tmp; /* Stop then Reset */ UOG_USBCMD &= ~UCMD_RUN_STOP; while (UOG_USBCMD & UCMD_RUN_STOP) ; UOG_USBCMD |= UCMD_RESET; while ((UOG_USBCMD) & (UCMD_RESET)) ; if (cpu_is_mx53()) USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_OC_DIS; if (cpu_is_mx51()) { if (machine_is_mx51_3ds()) { /* OTG Polarity of Overcurrent is Low active */ USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_OC_POL; /* Enable OTG Overcurrent Event */ USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_OC_DIS; } else { /* BBG is not using OC */ USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_OC_DIS; } } else if (cpu_is_mx25()) { USBCTRL |= UCTRL_OCPOL; USBCTRL &= ~UCTRL_PP; } else if (cpu_is_mx50()) { USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_OC_DIS; } else { /* USBOTG_PWR low active */ USBCTRL &= ~UCTRL_PP; /* OverCurrent Polarity is Low Active */ USBCTRL &= ~UCTRL_OCPOL; if (cpu_is_mx35_rev(CHIP_REV_2_0) < 0) /* OTG Lock Disable */ USBCTRL |= UCTRL_OLOCKD; } if (cpu_is_mx51()) USBCTRL &= ~UCTRL_OPM; /* OTG Power Mask */ USBCTRL &= ~UCTRL_OWIE; /* OTG Wakeup Intr Disable */ /* set UTMI xcvr */ tmp = UOG_PORTSC1 & ~PORTSC_PTS_MASK; tmp |= PORTSC_PTS_UTMI; UOG_PORTSC1 = tmp; if (cpu_is_mx51()) { /* Set the PHY clock to 19.2MHz */ USB_PHY_CTR_FUNC2 &= ~USB_UTMI_PHYCTRL2_PLLDIV_MASK; USB_PHY_CTR_FUNC2 |= 0x01; } else if (machine_is_mx37_3ds()) { /* Reference voltage for HS disconnect envelope detector */ /* adjust the Squelch level */ USB_PHY_CTR_FUNC2 &= ~(USB_UTMI_PHYCTRL2_HSDEVSEL_MASK << USB_UTMI_PHYCTRL2_HSDEVSEL_SHIFT); } /* Workaround an IC issue for ehci driver: * when turn off root hub port power, EHCI set * PORTSC reserved bits to be 0, but PTW with 0 * means 8 bits tranceiver width, here change * it back to be 16 bits and do PHY diable and * then enable. */ UOG_PORTSC1 |= PORTSC_PTW; if (cpu_is_mx35() || cpu_is_mx25()) { /* Enable UTMI interface in PHY control Reg */ USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_UTMI_ENABLE; USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_UTMI_ENABLE; } /* need to reset the controller here so that the ID pin * is correctly detected. */ /* Stop then Reset */ UOG_USBCMD &= ~UCMD_RUN_STOP; while (UOG_USBCMD & UCMD_RUN_STOP) ; UOG_USBCMD |= UCMD_RESET; while ((UOG_USBCMD) & (UCMD_RESET)) ; /* allow controller to reset, and leave time for * the ULPI transceiver to reset too. */ msleep(100); if (cpu_is_mx37()) { /* fix USB PHY Power Gating leakage issue for i.MX37 */ USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_CHGRDETON; USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_CHGRDETEN; } /* Turn off the usbpll for UTMI tranceivers */ clk_disable(usb_clk); }