static void mdss_dsi_clk_ctrl_sub(struct mdss_dsi_ctrl_pdata *ctrl, int enable)
{
int changed = 0;
if (enable) {
if (ctrl->clk_cnt_sub == 0)
changed++;
ctrl->clk_cnt_sub++;
} else {
if (ctrl->clk_cnt_sub) {
ctrl->clk_cnt_sub--;
if (ctrl->clk_cnt_sub == 0)
changed++;
} else {
pr_debug("%s: Can not be turned off\n", __func__);
}
}
pr_debug("%s: ndx=%d clk_cnt_sub=%d changed=%d enable=%d\n",
__func__, ctrl->ndx, ctrl->clk_cnt_sub, changed, enable);
if (changed) {
if (enable) {
if (mdss_dsi_bus_clk_start(ctrl) == 0)
mdss_dsi_link_clk_start(ctrl);
} else {
mdss_dsi_link_clk_stop(ctrl);
mdss_dsi_bus_clk_stop(ctrl);
}
}
}
static int mdss_dsi_clk_ctrl_sub(struct mdss_dsi_ctrl_pdata *ctrl,
u8 clk_type, int enable)
{
int rc = 0;
if (!ctrl) {
pr_err("%s: Invalid arg\n", __func__);
return -EINVAL;
}
pr_debug("%s: ndx=%d clk_type=%08x enable=%d\n", __func__,
ctrl->ndx, clk_type, enable);
if (enable) {
if (clk_type & DSI_BUS_CLKS) {
rc = mdss_dsi_bus_clk_start(ctrl);
if (rc) {
pr_err("Failed to start bus clocks. rc=%d\n",
rc);
goto error;
}
}
if (clk_type & DSI_LINK_CLKS) {
rc = mdss_dsi_link_clk_start(ctrl);
if (rc) {
pr_err("Failed to start link clocks. rc=%d\n",
rc);
if (clk_type & DSI_BUS_CLKS)
mdss_dsi_bus_clk_stop(ctrl);
goto error;
}
}
} else {
if (clk_type & DSI_LINK_CLKS)
mdss_dsi_link_clk_stop(ctrl);
if (clk_type & DSI_BUS_CLKS)
mdss_dsi_bus_clk_stop(ctrl);
}
error:
return rc;
}
/**
* mdss_dsi_core_power_ctrl() - Enable/disable DSI core power
* @ctrl: pointer to DSI controller structure
* @enable: 1 to enable power, 0 to disable power
*
* When all DSI bus clocks are disabled, DSI core power module can be turned
* off to save any leakage current. This function implements the necessary
* programming sequence for the same. For command mode panels, the core power
* can be turned off for idle-screen usecases, where additional programming is
* needed to clamp DSI phy.
*/
static int mdss_dsi_core_power_ctrl(struct mdss_dsi_ctrl_pdata *ctrl,
int enable)
{
int rc = 0;
struct mdss_panel_data *pdata = NULL;
if (!ctrl) {
pr_err("%s: invalid input\n", __func__);
return -EINVAL;
}
pdata = &ctrl->panel_data;
if (!pdata) {
pr_err("%s: Invalid panel data\n", __func__);
return -EINVAL;
}
if (enable) {
if (!ctrl->core_power) {
/* enable mdss gdsc */
pr_debug("%s: Enable MDP FS\n", __func__);
rc = msm_dss_enable_vreg(
ctrl->power_data[DSI_CORE_PM].vreg_config,
ctrl->power_data[DSI_CORE_PM].num_vreg, 1);
if (rc) {
pr_err("%s: failed to enable vregs for %s\n",
__func__,
__mdss_dsi_pm_name(DSI_CORE_PM));
goto error;
}
ctrl->core_power = true;
}
rc = mdss_dsi_bus_clk_start(ctrl);
if (rc) {
pr_err("%s: Failed to start bus clocks. rc=%d\n",
__func__, rc);
goto error_bus_clk_start;
}
/*
* Phy software reset should not be done for:
* 1.) Idle screen power collapse use-case. Issue a phy software
* reset only when unblanking the panel in this case.
* 2.) When ULPS during suspend is enabled.
*/
if (pdata->panel_info.blank_state == MDSS_PANEL_BLANK_BLANK &&
!pdata->panel_info.ulps_suspend_enabled)
mdss_dsi_phy_sw_reset(ctrl);
/*
* Phy and controller setup need not be done during bootup
* when continuous splash screen is enabled.
*/
if (!pdata->panel_info.cont_splash_enabled) {
mdss_dsi_phy_init(ctrl);
mdss_dsi_ctrl_setup(ctrl);
}
if (ctrl->ulps) {
/*
* ULPS Entry Request. This is needed if the lanes were
* in ULPS prior to power collapse, since after
* power collapse and reset, the DSI controller resets
* back to idle state and not ULPS. This ulps entry
* request will transition the state of the DSI
* controller to ULPS which will match the state of the
* DSI phy. This needs to be done prior to disabling
* the DSI clamps.
*
* Also, reset the ulps flag so that ulps_config
* function would reconfigure the controller state to
* ULPS.
*/
ctrl->ulps = false;
rc = mdss_dsi_ulps_config(ctrl, 1);
if (rc) {
pr_err("%s: Failed to enter ULPS. rc=%d\n",
__func__, rc);
goto error_ulps;
}
}
rc = mdss_dsi_clamp_ctrl(ctrl, 0);
if (rc) {
pr_err("%s: Failed to disable dsi clamps. rc=%d\n",
__func__, rc);
goto error_ulps;
}
} else {
/*
* Enable DSI clamps only if entering idle power collapse or
* when ULPS during suspend is enabled.
*/
if ((pdata->panel_info.blank_state != MDSS_PANEL_BLANK_BLANK) ||
pdata->panel_info.ulps_suspend_enabled) {
rc = mdss_dsi_clamp_ctrl(ctrl, 1);
if (rc)
pr_err("%s: Failed to enable dsi clamps. rc=%d\n",
__func__, rc);
}
/*
* disable bus clocks irrespective of whether dsi phy was
* successfully clamped or not
*/
mdss_dsi_bus_clk_stop(ctrl);
/* disable mdss gdsc only if dsi phy was successfully clamped*/
if (rc) {
pr_debug("%s: leaving mdss gdsc on\n", __func__);
} else {
pr_debug("%s: Disable MDP FS\n", __func__);
rc = msm_dss_enable_vreg(
ctrl->power_data[DSI_CORE_PM].vreg_config,
ctrl->power_data[DSI_CORE_PM].num_vreg, 0);
if (rc) {
pr_warn("%s: failed to disable vregs for %s\n",
__func__,
__mdss_dsi_pm_name(DSI_CORE_PM));
rc = 0;
} else {
ctrl->core_power = false;
}
}
}
return rc;
error_ulps:
mdss_dsi_bus_clk_stop(ctrl);
error_bus_clk_start:
if (msm_dss_enable_vreg(ctrl->power_data[DSI_CORE_PM].vreg_config,
ctrl->power_data[DSI_CORE_PM].num_vreg, 0))
pr_warn("%s: failed to disable vregs for %s\n",
__func__, __mdss_dsi_pm_name(DSI_CORE_PM));
else
ctrl->core_power = false;
error:
return rc;
}
static int mdss_dsi_clk_ctrl_sub(struct mdss_dsi_ctrl_pdata *ctrl,
u8 clk_type, int enable)
{
int rc = 0;
struct mdss_panel_data *pdata;
if (!ctrl) {
pr_err("%s: Invalid arg\n", __func__);
return -EINVAL;
}
pdata = &ctrl->panel_data;
pr_debug("%s: ndx=%d clk_type=%08x enable=%d\n", __func__,
ctrl->ndx, clk_type, enable);
if (enable) {
if (clk_type & DSI_BUS_CLKS) {
/* enable mdss gdsc */
pr_debug("%s: Enable MDP FS\n", __func__);
rc = msm_dss_enable_vreg(
ctrl->power_data[DSI_CORE_PM].vreg_config,
ctrl->power_data[DSI_CORE_PM].num_vreg, 1);
if (rc) {
pr_err("%s: failed to enable vregs for %s\n",
__func__,
__mdss_dsi_pm_name(DSI_CORE_PM));
goto error;
}
rc = mdss_dsi_bus_clk_start(ctrl);
if (rc) {
pr_err("Failed to start bus clocks. rc=%d\n",
rc);
goto error_vreg;
}
}
if (clk_type & DSI_LINK_CLKS) {
rc = mdss_dsi_link_clk_start(ctrl);
if (rc) {
pr_err("Failed to start link clocks. rc=%d\n",
rc);
goto error_link_clk_start;
}
/* Disable ULPS, if enabled */
if (ctrl->ulps) {
rc = mdss_dsi_ulps_config(ctrl, 0);
if (rc) {
pr_err("Failed to exit ulps. rc=%d\n",
rc);
goto error_ulps_exit;
}
}
}
} else {
if (clk_type & DSI_LINK_CLKS) {
/*
* If ULPS feature is enabled, enter ULPS first.
* No need to enable ULPS when turning off clocks
* while blanking the panel.
*/
if ((mdss_dsi_ulps_feature_enabled(pdata)) &&
(pdata->panel_info.panel_power_on))
mdss_dsi_ulps_config(ctrl, 1);
mdss_dsi_link_clk_stop(ctrl);
}
if (clk_type & DSI_BUS_CLKS) {
mdss_dsi_bus_clk_stop(ctrl);
/* disable mdss gdsc */
pr_debug("%s: Disable MDP FS\n", __func__);
rc = msm_dss_enable_vreg(
ctrl->power_data[DSI_CORE_PM].vreg_config,
ctrl->power_data[DSI_CORE_PM].num_vreg, 0);
if (rc) {
pr_warn("%s: failed to disable vregs for %s\n",
__func__,
__mdss_dsi_pm_name(DSI_CORE_PM));
rc = 0;
}
}
}
return rc;
error_ulps_exit:
mdss_dsi_link_clk_stop(ctrl);
error_link_clk_start:
if (clk_type & DSI_BUS_CLKS)
mdss_dsi_bus_clk_stop(ctrl);
error_vreg:
if ((clk_type & DSI_BUS_CLKS) &&
(msm_dss_enable_vreg(ctrl->power_data[DSI_CORE_PM].vreg_config,
ctrl->power_data[DSI_CORE_PM].num_vreg, 0))) {
pr_warn("%s: failed to disable vregs for %s\n", __func__,
__mdss_dsi_pm_name(DSI_CORE_PM));
}
error:
return rc;
}
int mdss_dsi_on(struct mdss_panel_data *pdata)
{
int ret = 0;
u32 clk_rate;
struct mdss_panel_info *pinfo;
struct mipi_panel_info *mipi;
u32 hbp, hfp, vbp, vfp, hspw, vspw, width, height;
u32 ystride, bpp, data, dst_bpp;
u32 dummy_xres, dummy_yres;
struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
u32 hsync_period, vsync_period;
if (pdata == NULL) {
pr_err("%s: Invalid input data\n", __func__);
return -EINVAL;
}
if (pdata->panel_info.panel_power_on) {
pr_warn("%s:%d Panel already on.\n", __func__, __LINE__);
return 0;
}
ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata,
panel_data);
pr_debug("%s+: ctrl=%p ndx=%d\n",
__func__, ctrl_pdata, ctrl_pdata->ndx);
pinfo = &pdata->panel_info;
ret = msm_dss_enable_vreg(ctrl_pdata->power_data.vreg_config,
ctrl_pdata->power_data.num_vreg, 1);
if (ret) {
pr_err("%s:Failed to enable vregs. rc=%d\n", __func__, ret);
return ret;
}
pdata->panel_info.panel_power_on = 1;
if (!pdata->panel_info.mipi.lp11_init)
mdss_dsi_panel_reset(pdata, 1);
ret = mdss_dsi_bus_clk_start(ctrl_pdata);
if (ret) {
pr_err("%s: failed to enable bus clocks. rc=%d\n", __func__,
ret);
mdss_dsi_panel_power_on(pdata, 0);
pdata->panel_info.panel_power_on = 0;
return ret;
}
mdss_dsi_phy_sw_reset((ctrl_pdata->ctrl_base));
mdss_dsi_phy_init(pdata);
mdss_dsi_bus_clk_stop(ctrl_pdata);
mdss_dsi_clk_ctrl(ctrl_pdata, 1);
clk_rate = pdata->panel_info.clk_rate;
clk_rate = min(clk_rate, pdata->panel_info.clk_max);
dst_bpp = pdata->panel_info.fbc.enabled ?
(pdata->panel_info.fbc.target_bpp) : (pinfo->bpp);
hbp = mult_frac(pdata->panel_info.lcdc.h_back_porch, dst_bpp,
pdata->panel_info.bpp);
hfp = mult_frac(pdata->panel_info.lcdc.h_front_porch, dst_bpp,
pdata->panel_info.bpp);
vbp = mult_frac(pdata->panel_info.lcdc.v_back_porch, dst_bpp,
pdata->panel_info.bpp);
vfp = mult_frac(pdata->panel_info.lcdc.v_front_porch, dst_bpp,
pdata->panel_info.bpp);
hspw = mult_frac(pdata->panel_info.lcdc.h_pulse_width, dst_bpp,
pdata->panel_info.bpp);
vspw = pdata->panel_info.lcdc.v_pulse_width;
width = mult_frac(pdata->panel_info.xres, dst_bpp,
pdata->panel_info.bpp);
height = pdata->panel_info.yres;
if (pdata->panel_info.type == MIPI_VIDEO_PANEL) {
dummy_xres = pdata->panel_info.lcdc.xres_pad;
dummy_yres = pdata->panel_info.lcdc.yres_pad;
}
vsync_period = vspw + vbp + height + dummy_yres + vfp;
hsync_period = hspw + hbp + width + dummy_xres + hfp;
mipi = &pdata->panel_info.mipi;
if (pdata->panel_info.type == MIPI_VIDEO_PANEL) {
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x24,
((hspw + hbp + width + dummy_xres) << 16 |
(hspw + hbp)));
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x28,
((vspw + vbp + height + dummy_yres) << 16 |
(vspw + vbp)));
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x2C,
((vsync_period - 1) << 16)
| (hsync_period - 1));
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x30, (hspw << 16));
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x34, 0);
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x38, (vspw << 16));
} else { /* command mode */
if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB888)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB666)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB565)
bpp = 2;
else
bpp = 3; /* Default format set to RGB888 */
ystride = width * bpp + 1;
/* DSI_COMMAND_MODE_MDP_STREAM_CTRL */
data = (ystride << 16) | (mipi->vc << 8) | DTYPE_DCS_LWRITE;
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x60, data);
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x58, data);
/* DSI_COMMAND_MODE_MDP_STREAM_TOTAL */
data = height << 16 | width;
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x64, data);
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x5C, data);
}
mdss_dsi_sw_reset(pdata);
mdss_dsi_host_init(mipi, pdata);
/*
* Issue hardware reset line after enabling the DSI clocks and data
* data lanes for LP11 init
*/
if (pdata->panel_info.mipi.lp11_init)
mdss_dsi_panel_reset(pdata, 1);
if (pdata->panel_info.mipi.init_delay)
usleep(pdata->panel_info.mipi.init_delay);
if (mipi->force_clk_lane_hs) {
u32 tmp;
tmp = MIPI_INP((ctrl_pdata->ctrl_base) + 0xac);
tmp |= (1<<28);
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0xac, tmp);
wmb();
}
if (pdata->panel_info.type == MIPI_CMD_PANEL)
mdss_dsi_clk_ctrl(ctrl_pdata, 0);
pr_debug("%s-:\n", __func__);
return 0;
}
static int mdss_dsi_clk_ctrl_sub(struct mdss_dsi_ctrl_pdata *ctrl,
u8 clk_type, int enable)
{
int rc = 0;
struct mdss_panel_data *pdata;
if (!ctrl) {
pr_err("%s: Invalid arg\n", __func__);
return -EINVAL;
}
pdata = &ctrl->panel_data;
pr_debug("%s: ndx=%d clk_type=%08x enable=%d\n", __func__,
ctrl->ndx, clk_type, enable);
if (enable) {
if (clk_type & DSI_BUS_CLKS) {
/* enable mdss gdsc */
pr_debug("%s: Enable MDP FS\n", __func__);
rc = msm_dss_enable_vreg(
ctrl->power_data[DSI_CORE_PM].vreg_config,
ctrl->power_data[DSI_CORE_PM].num_vreg, 1);
if (rc) {
pr_err("%s: failed to enable vregs for %s\n",
__func__,
__mdss_dsi_pm_name(DSI_CORE_PM));
goto error;
}
rc = mdss_dsi_bus_clk_start(ctrl);
if (rc) {
pr_err("Failed to start bus clocks. rc=%d\n",
rc);
goto error_vreg;
}
}
if (clk_type & DSI_LINK_CLKS) {
if (ctrl->mmss_clamp) {
mdss_dsi_phy_init(pdata);
mdss_dsi_ctrl_setup(pdata);
mdss_dsi_host_init(pdata);
mdss_dsi_op_mode_config(pdata->panel_info.mipi.mode,
pdata);
/*
* ULPS Entry Request. This is needed because, after power
* collapse and reset, the DSI controller resets back to
* idle state and not ULPS.
*/
mdss_dsi_ulps_config(ctrl, 1);
mdss_dsi_clamp_ctrl(ctrl, 0);
}
rc = mdss_dsi_link_clk_start(ctrl);
if (rc) {
pr_err("Failed to start link clocks. rc=%d\n",
rc);
goto error_link_clk_start;
}
/* Disable ULPS, if enabled */
if (ctrl->ulps) {
rc = mdss_dsi_ulps_config(ctrl, 0);
if (rc) {
pr_err("Failed to exit ulps. rc=%d\n",
rc);
goto error_ulps_exit;
}
}
}
} else {
if (clk_type & DSI_LINK_CLKS) {
/*
* If ULPS feature is enabled, enter ULPS first.
* No need to enable ULPS when turning off clocks
* while blanking the panel.
*/
if (((mdss_dsi_ulps_feature_enabled(pdata)) &&
(pdata->panel_info.panel_power_on)) ||
(pdata->panel_info.ulps_suspend_enabled &&
!pdata->panel_info.panel_power_on)) {
mdss_dsi_ulps_config(ctrl, 1);
mdss_dsi_link_clk_stop(ctrl);
mdss_dsi_clamp_ctrl(ctrl, 1);
} else {
mdss_dsi_link_clk_stop(ctrl);
}
}
if (clk_type & DSI_BUS_CLKS) {
mdss_dsi_bus_clk_stop(ctrl);
/* disable mdss gdsc */
pr_debug("%s: Disable MDP FS\n", __func__);
rc = msm_dss_enable_vreg(
ctrl->power_data[DSI_CORE_PM].vreg_config,
ctrl->power_data[DSI_CORE_PM].num_vreg, 0);
if (rc) {
pr_warn("%s: failed to disable vregs for %s\n",
__func__,
__mdss_dsi_pm_name(DSI_CORE_PM));
rc = 0;
}
}
}
return rc;
error_ulps_exit:
mdss_dsi_link_clk_stop(ctrl);
error_link_clk_start:
if (clk_type & DSI_BUS_CLKS)
mdss_dsi_bus_clk_stop(ctrl);
error_vreg:
if ((clk_type & DSI_BUS_CLKS) &&
(msm_dss_enable_vreg(ctrl->power_data[DSI_CORE_PM].vreg_config,
ctrl->power_data[DSI_CORE_PM].num_vreg, 0))) {
pr_warn("%s: failed to disable vregs for %s\n", __func__,
__mdss_dsi_pm_name(DSI_CORE_PM));
}
error:
return rc;
}
/**
* mdss_dsi_core_power_ctrl() - Enable/disable DSI core power
* @ctrl: pointer to DSI controller structure
* @enable: 1 to enable power, 0 to disable power
*
* When all DSI bus clocks are disabled, DSI core power module can be turned
* off to save any leakage current. This function implements the necessary
* programming sequence for the same. For command mode panels, the core power
* can be turned off for idle-screen usecases, where additional programming is
* needed to clamp DSI phy.
*/
static int mdss_dsi_core_power_ctrl(struct mdss_dsi_ctrl_pdata *ctrl,
int enable)
{
int rc = 0;
struct mdss_panel_data *pdata = NULL;
u32 ctrl_rev;
if (!ctrl) {
pr_err("%s: invalid input\n", __func__);
return -EINVAL;
}
pdata = &ctrl->panel_data;
if (!pdata) {
pr_err("%s: Invalid panel data\n", __func__);
return -EINVAL;
}
if (enable) {
if (!ctrl->core_power) {
/* enable mdss gdsc */
pr_debug("%s: Enable MDP FS\n", __func__);
rc = msm_dss_enable_vreg(
ctrl->power_data[DSI_CORE_PM].vreg_config,
ctrl->power_data[DSI_CORE_PM].num_vreg, 1);
if (rc) {
pr_err("%s: failed to enable vregs for %s\n",
__func__,
__mdss_dsi_pm_name(DSI_CORE_PM));
goto error;
}
ctrl->core_power = true;
}
/*
* temp workaround until framework issues pertaining to LP2
* power state transitions are fixed. For now, if we intend to
* send a frame update when in LP1, we have to explicitly exit
* LP2 state here
*/
if (mdss_dsi_is_panel_on_ulp(pdata))
mdss_dsi_panel_power_ctrl(pdata, MDSS_PANEL_POWER_LP1);
rc = mdss_dsi_bus_clk_start(ctrl);
if (rc) {
pr_err("%s: Failed to start bus clocks. rc=%d\n",
__func__, rc);
goto error_bus_clk_start;
}
/*
* Phy and controller setup is needed if coming out of idle
* power collapse with clamps enabled.
*/
if (ctrl->mmss_clamp) {
ctrl_rev = MIPI_INP(ctrl->ctrl_base);
if (ctrl_rev == MDSS_DSI_HW_REV_103)
mdss_dsi_20nm_phy_init(pdata);
else
mdss_dsi_phy_init(pdata);
mdss_dsi_ctrl_setup(ctrl);
}
if (ctrl->ulps) {
/*
* ULPS Entry Request. This is needed if the lanes were
* in ULPS prior to power collapse, since after
* power collapse and reset, the DSI controller resets
* back to idle state and not ULPS. This ulps entry
* request will transition the state of the DSI
* controller to ULPS which will match the state of the
* DSI phy. This needs to be done prior to disabling
* the DSI clamps.
*
* Also, reset the ulps flag so that ulps_config
* function would reconfigure the controller state to
* ULPS.
*/
ctrl->ulps = false;
rc = mdss_dsi_ulps_config(ctrl, 1);
if (rc) {
pr_err("%s: Failed to enter ULPS. rc=%d\n",
__func__, rc);
goto error_ulps;
}
}
rc = mdss_dsi_clamp_ctrl(ctrl, 0);
if (rc) {
pr_err("%s: Failed to disable dsi clamps. rc=%d\n",
__func__, rc);
goto error_ulps;
}
} else {
/* Enable DSI clamps only if entering idle power collapse */
if (pdata->panel_info.blank_state != MDSS_PANEL_BLANK_BLANK) {
rc = mdss_dsi_clamp_ctrl(ctrl, 1);
if (rc)
pr_err("%s: Failed to enable dsi clamps. rc=%d\n",
__func__, rc);
} else {
/*
* Make sure that controller is not in ULPS state when
* the DSI link is not active.
*/
rc = mdss_dsi_ulps_config(ctrl, 0);
if (rc)
pr_err("%s: failed to disable ulps. rc=%d\n",
__func__, rc);
}
/*
* disable bus clocks irrespective of whether dsi phy was
* successfully clamped or not
*/
mdss_dsi_bus_clk_stop(ctrl);
/* disable mdss gdsc only if dsi phy was successfully clamped*/
if (rc) {
pr_debug("%s: leaving mdss gdsc on\n", __func__);
} else {
pr_debug("%s: Disable MDP FS\n", __func__);
rc = msm_dss_enable_vreg(
ctrl->power_data[DSI_CORE_PM].vreg_config,
ctrl->power_data[DSI_CORE_PM].num_vreg, 0);
if (rc) {
pr_warn("%s: failed to disable vregs for %s\n",
__func__,
__mdss_dsi_pm_name(DSI_CORE_PM));
rc = 0;
} else {
ctrl->core_power = false;
}
}
/*
* temp workaround until framework issues pertaining to LP2
* power state transitions are fixed. For now, we internally
* transition to LP2 state whenever core power is turned off
* in LP1 state
*/
if (mdss_dsi_is_panel_on_lp(pdata))
mdss_dsi_panel_power_ctrl(pdata, MDSS_PANEL_POWER_LP2);
}
return rc;
error_ulps:
mdss_dsi_bus_clk_stop(ctrl);
error_bus_clk_start:
if (msm_dss_enable_vreg(ctrl->power_data[DSI_CORE_PM].vreg_config,
ctrl->power_data[DSI_CORE_PM].num_vreg, 0))
pr_warn("%s: failed to disable vregs for %s\n",
__func__, __mdss_dsi_pm_name(DSI_CORE_PM));
else
ctrl->core_power = false;
error:
return rc;
}
