static void sync()
{
mem_setprg16(0x8,outerprg | prg);
mem_setprg16(0xC,outerprg | (0xFF & prgmask));
mem_setvram8(0,0);
mem_setmirroring(mirroring);
}
static void sync()
{
static u8 oldreg1 = 0x10;
u8 reg1 = mmc1_getlowchr();
mmc1_syncmirror();
mmc1_syncsram();
mem_setvram8(0,0);
if(reg1 & 0x10) {
irqenabled = 0;
irqcounter = 0;
cpu_clear_irq(IRQ_MAPPER);
}
else
irqenabled = 1;
if(prglock) {
mem_setprg32(8,0);
if((oldreg1 & 0x10) == 0 && (reg1 & 0x10) == 0x10)
prglock = 0;
}
else {
if(reg1 & 8)
mmc1_syncprg(7,8);
else
mem_setprg32(8,(reg1 >> 1) & 3);
}
oldreg1 = reg1;
}
static void sync()
{
mem_setprg16(0x8,reg[1]);
mem_setprg16(0xC,0xFF);
mem_setvram8(0,0);
ppu_setmirroring((reg[0] & 0x10) ? MIRROR_1H : MIRROR_1L);
}
static void sync()
{
mem_setprg32(8,prg);
mem_setvram8(0,0);
switch(mirror) {
case 0: ppu_setmirroring(MIRROR_H); break;
case 1: ppu_setmirroring(MIRROR_V); break;
case 2: ppu_setmirroring(MIRROR_1L); break;
case 3: ppu_setmirroring(MIRROR_1H); break;
}
}
static void sync()
{
switch(mode) {
case 0x00:
case 0x10:
mem_setprg16(0x8,bankhi | banklo);
mem_setprg16(0xC,bankhi | 7);
break;
case 0x20:
mem_setprg32(0x8,(bankhi | banklo) >> 1);
break;
case 0x30:
mem_setprg16(0x8,bankhi | banklo);
mem_setprg16(0xC,bankhi | banklo);
break;
}
if(revision == BMC_70IN1)
mem_setchr8(0,chrbank);
else
mem_setvram8(0,0);
mem_setmirroring(mirror);
}
static void sync()
{
mem_setprg32(8,latch_reg);
mem_setvram8(0,0);
}
