/*
 * If hardware detected a change in impedance and raised an INTR
 * We check the range of this impedance to infer if the connected
 * device is MHL or USB and take appropriate actions.
 */
static int  mhl_msm_read_rgnd_int(void)
{
	uint8_t rgnd_imp;

	/*
	 * DISC STATUS REG 2
	 * 1:0 RGND
	 * 00  - open (USB)
	 * 01  - 2 kOHM (USB)
	 * 10  - 1 kOHM ***(MHL)**** It's range 800 - 1200 OHM from MHL spec
	 * 11  - short (USB)
	 */
	rgnd_imp = (mhl_i2c_reg_read(TX_PAGE_3, 0x001C) & (BIT1 | BIT0));
	pr_debug("Imp Range read = %02X\n", (int)rgnd_imp);

	if (0x02 == rgnd_imp) {
		pr_debug("MHL: MHL DEVICE!!!\n");
		mhl_i2c_reg_modify(TX_PAGE_3, 0x0018, BIT0, BIT0);
		mhl_msm_state->mhl_mode = TRUE;
		if (notify_usb_online)
			notify_usb_online(1);
	} else {
		pr_debug("MHL: NON-MHL DEVICE!!!\n");
		mhl_msm_state->mhl_mode = FALSE;
		mhl_i2c_reg_modify(TX_PAGE_3, 0x0018, BIT3, BIT3);
		switch_mode(POWER_STATE_D3);
	}
	complete(&mhl_msm_state->rgnd_done);
	return mhl_msm_state->mhl_mode ?
		MHL_DISCOVERY_RESULT_MHL : MHL_DISCOVERY_RESULT_USB;
}
static int mhl_msc_command_done(struct msc_command_struct *req)
{
	switch (req->command) {
	case MHL_WRITE_STAT:
		if (req->offset == MHL_STATUS_REG_LINK_MODE) {
			if (req->payload.data[0]
				& MHL_STATUS_PATH_ENABLED) {
				
				mhl_i2c_reg_modify(TX_PAGE_L0, 0x0080,
								BIT4, BIT4);
			} else
				
				mhl_i2c_reg_modify(TX_PAGE_L0, 0x0080,
								BIT4, BIT4);
		}
		break;
	case MHL_READ_DEVCAP:
		mhl_msm_state->devcap_state |= BIT(req->offset);
		switch (req->offset) {
		case MHL_DEV_CATEGORY_OFFSET:
			if (req->retval & MHL_DEV_CATEGORY_POW_BIT) {
			} else {
			}
			break;
		case DEVCAP_OFFSET_MHL_VERSION:
		case DEVCAP_OFFSET_INT_STAT_SIZE:
			break;
		}

		break;
	}
	return 0;
}
static void cbus_reset(void)
{
	uint8_t i;

	mhl_i2c_reg_modify(TX_PAGE_3, 0x0000, BIT3, BIT3);
	msleep(20);
	mhl_i2c_reg_modify(TX_PAGE_3, 0x0000, BIT3, 0x00);
	mhl_i2c_reg_write(TX_PAGE_L0, 0x0075, BIT6);
	mhl_i2c_reg_write(TX_PAGE_3, 0x0022,
		BIT0 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6);
	
	if (mhl_msm_state->chip_rev_id < 1)
		mhl_i2c_reg_write(TX_PAGE_3, 0x0024, BIT3 | BIT4);
	else
		
		mhl_i2c_reg_write(TX_PAGE_3, 0x0024, 0x00);

	
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0009,
		BIT2 | BIT3 | BIT4 | BIT5 | BIT6);

	
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x001F, BIT2 | BIT3);

	for (i = 0; i < 4; i++) {
		mhl_i2c_reg_write(TX_PAGE_CBUS, (0xE0 + i), 0xFF);

		mhl_i2c_reg_write(TX_PAGE_CBUS, (0xF0 + i), 0xFF);
	}
}
static void switch_mode(enum mhl_st_type to_mode)
{
	unsigned long flags;

	switch (to_mode) {
	case POWER_STATE_D0_NO_MHL:
		break;
	case POWER_STATE_D0_MHL:
		mhl_init_reg_settings(true);
		
		mhl_i2c_reg_modify(TX_PAGE_3, 0x0010, BIT1 | BIT0, BIT0);

		mhl_i2c_reg_modify(TX_PAGE_TPI, 0x001E, BIT1 | BIT0, 0x00);
		break;
	case POWER_STATE_D3:
		if (mhl_msm_state->cur_state != POWER_STATE_D3) {
			
			mhl_drive_hpd(HPD_DOWN);
			mhl_i2c_reg_write(TX_PAGE_3, 0x0030, 0xD0);
			msleep(50);
			mhl_i2c_reg_modify(TX_PAGE_3, 0x0010,
				BIT1 | BIT0, 0x00);
			mhl_i2c_reg_modify(TX_PAGE_3, 0x003D, BIT0, 0x00);
			spin_lock_irqsave(&mhl_state_lock, flags);
			mhl_msm_state->cur_state = POWER_STATE_D3;
			spin_unlock_irqrestore(&mhl_state_lock, flags);
		}
		break;
	default:
		break;
	}
}
Beispiel #5
0
static void force_usb_switch_open(void)
{
	/*DISABLE_DISCOVERY*/
	mhl_i2c_reg_modify(TX_PAGE_3, 0x0010, BIT0, 0);
	/* Force USB ID switch to open*/
	mhl_i2c_reg_modify(TX_PAGE_3, 0x0015, BIT6, BIT6);
	mhl_i2c_reg_write(TX_PAGE_3, 0x0012, 0x86);
	/* Force HPD to 0 when not in Mobile HD mode. */
	mhl_i2c_reg_modify(TX_PAGE_3, 0x0020, BIT5 | BIT4, BIT4);
}
static void force_usb_switch_open(void)
{
	
	mhl_i2c_reg_modify(TX_PAGE_3, 0x0010, BIT0, 0);
	
	mhl_i2c_reg_modify(TX_PAGE_3, 0x0015, BIT6, BIT6);
	mhl_i2c_reg_write(TX_PAGE_3, 0x0012, 0x86);
	
	mhl_i2c_reg_modify(TX_PAGE_3, 0x0020, BIT5 | BIT4, BIT4);
}
static int mhl_rap_action(u8 action_code)
{
	switch (action_code) {
	case MHL_RAP_CONTENT_ON:
		mhl_i2c_reg_modify(TX_PAGE_L0, 0x0080, BIT4, BIT4);
		break;
	case MHL_RAP_CONTENT_OFF:
		mhl_i2c_reg_modify(TX_PAGE_L0, 0x0080, BIT4, 0x00);
		break;
	default:
		break;
	}
	return 0;
}
static void switch_mode(struct mhl_tx_ctrl *mhl_ctrl, enum mhl_st_type to_mode,
			bool hpd_off)
{
	struct i2c_client *client = mhl_ctrl->i2c_handle;
	unsigned long flags;
	int rc;
	struct msm_hdmi_mhl_ops *hdmi_mhl_ops = mhl_ctrl->hdmi_mhl_ops;

	pr_debug("%s: tx pwr on\n", __func__);
	spin_lock_irqsave(&mhl_ctrl->lock, flags);
	mhl_ctrl->tx_powered_off = false;
	spin_unlock_irqrestore(&mhl_ctrl->lock, flags);

	switch (to_mode) {
	case POWER_STATE_D0_NO_MHL:
		mhl_ctrl->cur_state = to_mode;
		mhl_init_reg_settings(mhl_ctrl, true);
		/* REG_DISC_CTRL1 */
		MHL_SII_REG_NAME_MOD(REG_DISC_CTRL1, BIT1 | BIT0, BIT0);

		/* TPI_DEVICE_POWER_STATE_CTRL_REG */
		mhl_i2c_reg_modify(client, TX_PAGE_TPI, 0x001E, BIT1 | BIT0,
			0x00);
		break;
	case POWER_STATE_D0_MHL:
		mhl_ctrl->cur_state = to_mode;
		break;
	case POWER_STATE_D3:
		if (mhl_ctrl->cur_state == POWER_STATE_D3) {
			pr_debug("%s: mhl tx already in low power mode\n",
				__func__);
			break;
		}

		/* Force HPD to 0 when not in MHL mode.  */
		mhl_drive_hpd(mhl_ctrl, HPD_DOWN);
		mhl_tmds_ctrl(mhl_ctrl, TMDS_DISABLE);
		/*
		 * Change TMDS termination to high impedance
		 * on disconnection.
		 */
		MHL_SII_REG_NAME_WR(REG_MHLTX_CTL1, 0xD0);
		msleep(50);
		if (!mhl_ctrl->disc_enabled)
			MHL_SII_REG_NAME_MOD(REG_DISC_CTRL1, BIT1 | BIT0, 0x00);
		if (hdmi_mhl_ops && hpd_off) {
			rc = hdmi_mhl_ops->set_upstream_hpd(
				mhl_ctrl->pdata->hdmi_pdev, 0);
			pr_debug("%s: hdmi unset hpd %s\n", __func__,
				 rc ? "failed" : "passed");
		}
		mhl_ctrl->cur_state = POWER_STATE_D3;
		break;
	default:
		break;
	}
}
Beispiel #9
0
static void cbus_reset(void)
{
	uint8_t i;

	/*
	 * REG_SRST
	 */
	mhl_i2c_reg_modify(TX_PAGE_3, 0x0000, BIT3, BIT3);
	msleep(20);
	mhl_i2c_reg_modify(TX_PAGE_3, 0x0000, BIT3, 0x00);
	/*
	 * REG_INTR1 and REG_INTR4
	 */
	mhl_i2c_reg_write(TX_PAGE_L0, 0x0075, BIT6);
	mhl_i2c_reg_write(TX_PAGE_3, 0x0022,
		BIT0 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6);
	/* REG5 */
	if (mhl_msm_state->chip_rev_id < 1)
		mhl_i2c_reg_write(TX_PAGE_3, 0x0024, BIT3 | BIT4);
	else
		/*REG5 Mask disabled due to auto FIFO reset ??*/
		mhl_i2c_reg_write(TX_PAGE_3, 0x0024, 0x00);

	/* Unmask CBUS1 Intrs */
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0009,
		BIT2 | BIT3 | BIT4 | BIT5 | BIT6);

	/* Unmask CBUS2 Intrs */
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x001F, BIT2 | BIT3);

	for (i = 0; i < 4; i++) {
		/*
		 * Enable WRITE_STAT interrupt for writes to
		 * all 4 MSC Status registers.
		 */
		mhl_i2c_reg_write(TX_PAGE_CBUS, (0xE0 + i), 0xFF);

		/*
		 * Enable SET_INT interrupt for writes to
		 * all 4 MSC Interrupt registers.
		 */
		mhl_i2c_reg_write(TX_PAGE_CBUS, (0xF0 + i), 0xFF);
	}
}
static void init_cbus_regs(void)
{
	uint8_t		regval;

	
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0007, 0xF2);
	
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0036, 0x03);
	
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0039, 0x30);
	
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0040, 0x03);
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0080 | DEVCAP_OFFSET_DEV_STATE,
		DEVCAP_VAL_DEV_STATE);
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0080 | DEVCAP_OFFSET_MHL_VERSION,
		DEVCAP_VAL_MHL_VERSION);
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0080 | DEVCAP_OFFSET_DEV_CAT,
		DEVCAP_VAL_DEV_CAT);
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0080 | DEVCAP_OFFSET_ADOPTER_ID_H,
		DEVCAP_VAL_ADOPTER_ID_H);
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0080 | DEVCAP_OFFSET_ADOPTER_ID_L,
		DEVCAP_VAL_ADOPTER_ID_L);
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0080 | DEVCAP_OFFSET_VID_LINK_MODE,
		DEVCAP_VAL_VID_LINK_MODE);
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0080 | DEVCAP_OFFSET_AUD_LINK_MODE,
		DEVCAP_VAL_AUD_LINK_MODE);
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0080 | DEVCAP_OFFSET_VIDEO_TYPE,
		DEVCAP_VAL_VIDEO_TYPE);
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0080 | DEVCAP_OFFSET_LOG_DEV_MAP,
		DEVCAP_VAL_LOG_DEV_MAP);
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0080 | DEVCAP_OFFSET_BANDWIDTH,
		DEVCAP_VAL_BANDWIDTH);
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0080 | DEVCAP_OFFSET_FEATURE_FLAG,
		DEVCAP_VAL_FEATURE_FLAG);
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0080 | DEVCAP_OFFSET_DEVICE_ID_H,
		DEVCAP_VAL_DEVICE_ID_H);
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0080 | DEVCAP_OFFSET_DEVICE_ID_L,
		DEVCAP_VAL_DEVICE_ID_L);
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0080 | DEVCAP_OFFSET_SCRATCHPAD_SIZE,
		DEVCAP_VAL_SCRATCHPAD_SIZE);
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0080 | DEVCAP_OFFSET_INT_STAT_SIZE,
		DEVCAP_VAL_INT_STAT_SIZE);
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0080 | DEVCAP_OFFSET_RESERVED,
		DEVCAP_VAL_RESERVED);

	regval = mhl_i2c_reg_read(TX_PAGE_CBUS, 0x0031);
	regval = (regval | 0x0C);
	
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0031, regval);
	 
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0022, 0x0F);
	
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0030, 0x01);
	
	mhl_i2c_reg_modify(TX_PAGE_CBUS, 0x002E, BIT4, BIT4);
}
Beispiel #11
0
static int mhl_rap_action(u8 action_code)
{
	switch (action_code) {
	case MHL_RAP_CONTENT_ON:
		/*
		 * Enable TMDS on TMDS_CCTRL
		 */
		mhl_i2c_reg_modify(TX_PAGE_L0, 0x0080, BIT4, BIT4);
		break;
	case MHL_RAP_CONTENT_OFF:
		/*
		 * Disable TMDS on TMDS_CCTRL
		 */
		mhl_i2c_reg_modify(TX_PAGE_L0, 0x0080, BIT4, 0x00);
		break;
	default:
		break;
	}
	return 0;
}
static void mhl_drive_hpd(uint8_t to_state)
{
	if (mhl_msm_state->cur_state != POWER_STATE_D0_MHL) {
		pr_err("MHL: invalid state to ctrl HPD\n");
		return;
	}

	pr_debug("%s: To state=[0x%x]\n", __func__, to_state);
	if (to_state == HPD_UP) {

		
		mhl_i2c_reg_modify(TX_PAGE_L0, 0x0080, BIT4, BIT4);

		mhl_i2c_reg_modify(TX_PAGE_3, 0x0020, BIT4, 0x00);
	} else {
		mhl_i2c_reg_modify(TX_PAGE_3, 0x20, BIT4 | BIT5, BIT4);
		mhl_i2c_reg_modify(TX_PAGE_L0, 0x0080, BIT4, 0x00);
	}
	return;
}
Beispiel #13
0
static void switch_mode(enum mhl_st_type to_mode)
{
	unsigned long flags;

	switch (to_mode) {
	case POWER_STATE_D0_NO_MHL:
		break;
	case POWER_STATE_D0_MHL:
		mhl_init_reg_settings(true);
		/* REG_DISC_CTRL1 */
		mhl_i2c_reg_modify(TX_PAGE_3, 0x0010, BIT1 | BIT0, BIT0);

		/*
		 * TPI_DEVICE_POWER_STATE_CTRL_REG
		 * TX_POWER_STATE_MASK = BIT1 | BIT0
		 */
		mhl_i2c_reg_modify(TX_PAGE_TPI, 0x001E, BIT1 | BIT0, 0x00);
		break;
	case POWER_STATE_D3:
		if (mhl_msm_state->cur_state != POWER_STATE_D3) {
			/* Force HPD to 0 when not in MHL mode.  */
			mhl_drive_hpd(HPD_DOWN);
			/*
			 * Change TMDS termination to high impedance
			 * on disconnection.
			 */
			mhl_i2c_reg_write(TX_PAGE_3, 0x0030, 0xD0);
			msleep(50);
			mhl_i2c_reg_modify(TX_PAGE_3, 0x0010,
				BIT1 | BIT0, 0x00);
			mhl_i2c_reg_modify(TX_PAGE_3, 0x003D, BIT0, 0x00);
			spin_lock_irqsave(&mhl_state_lock, flags);
			mhl_msm_state->cur_state = POWER_STATE_D3;
			spin_unlock_irqrestore(&mhl_state_lock, flags);
		}
		break;
	default:
		break;
	}
}
static int  mhl_msm_read_rgnd_int(void)
{
	uint8_t rgnd_imp;

	rgnd_imp = (mhl_i2c_reg_read(TX_PAGE_3, 0x001C) & (BIT1 | BIT0));
	pr_debug("Imp Range read = %02X\n", (int)rgnd_imp);

	if (0x02 == rgnd_imp) {
		pr_debug("MHL: MHL DEVICE!!!\n");
		mhl_i2c_reg_modify(TX_PAGE_3, 0x0018, BIT0, BIT0);
		mhl_msm_state->mhl_mode = TRUE;
		if (notify_usb_online)
			notify_usb_online(1);
	} else {
		pr_debug("MHL: NON-MHL DEVICE!!!\n");
		mhl_msm_state->mhl_mode = FALSE;
		mhl_i2c_reg_modify(TX_PAGE_3, 0x0018, BIT3, BIT3);
		switch_mode(POWER_STATE_D3);
	}
	complete(&mhl_msm_state->rgnd_done);
	return mhl_msm_state->mhl_mode ?
		MHL_DISCOVERY_RESULT_MHL : MHL_DISCOVERY_RESULT_USB;
}
Beispiel #15
0
static void mhl_drive_hpd(uint8_t to_state)
{
	if (mhl_msm_state->cur_state != POWER_STATE_D0_MHL) {
		pr_err("MHL: invalid state to ctrl HPD\n");
		return;
	}

	pr_debug("%s: To state=[0x%x]\n", __func__, to_state);
	if (to_state == HPD_UP) {
		/*
		 * Drive HPD to UP state
		 *
		 * The below two reg configs combined
		 * enable TMDS output.
		 */

		/* Enable TMDS on TMDS_CCTRL */
		mhl_i2c_reg_modify(TX_PAGE_L0, 0x0080, BIT4, BIT4);

		/*
		 * Set HPD_OUT_OVR_EN = HPD State
		 * EDID read and Un-force HPD (from low)
		 * propogate to src let HPD float by clearing
		 * HPD OUT OVRRD EN
		 */
		mhl_i2c_reg_modify(TX_PAGE_3, 0x0020, BIT4, 0x00);
	} else {
		/*
		 * Drive HPD to DOWN state
		 * Disable TMDS Output on REG_TMDS_CCTRL
		 * Enable/Disable TMDS output (MHL TMDS output only)
		 */
		mhl_i2c_reg_modify(TX_PAGE_3, 0x20, BIT4 | BIT5, BIT4);
		mhl_i2c_reg_modify(TX_PAGE_L0, 0x0080, BIT4, 0x00);
	}
	return;
}
Beispiel #16
0
static void switch_mode(struct mhl_tx_ctrl *mhl_ctrl, enum mhl_st_type to_mode)
{
	struct i2c_client *client = mhl_ctrl->i2c_handle;

	switch (to_mode) {
	case POWER_STATE_D0_NO_MHL:
		mhl_ctrl->cur_state = to_mode;
		mhl_init_reg_settings(mhl_ctrl, true);
		/* REG_DISC_CTRL1 */
		MHL_SII_REG_NAME_MOD(REG_DISC_CTRL1, BIT1 | BIT0, BIT0);

		/* TPI_DEVICE_POWER_STATE_CTRL_REG */
		mhl_i2c_reg_modify(client, TX_PAGE_TPI, 0x001E, BIT1 | BIT0,
			0x00);
		break;
	case POWER_STATE_D0_MHL:
		mhl_ctrl->cur_state = to_mode;
		break;
	case POWER_STATE_D3:
		if (mhl_ctrl->cur_state == POWER_STATE_D3)
			break;

		/* Force HPD to 0 when not in MHL mode.  */
		mhl_drive_hpd(mhl_ctrl, HPD_DOWN);
		/*
		 * Change TMDS termination to high impedance
		 * on disconnection.
		 */
		MHL_SII_REG_NAME_WR(REG_MHLTX_CTL1, 0xD0);
		msleep(50);
		if (!mhl_ctrl->disc_enabled)
			MHL_SII_REG_NAME_MOD(REG_DISC_CTRL1, BIT1 | BIT0, 0x00);
		MHL_SII_PAGE3_MOD(0x003D, BIT0, 0x00);
		mhl_ctrl->cur_state = POWER_STATE_D3;
		break;
	default:
		break;
	}
}
Beispiel #17
0
static void release_usb_switch_open(void)
{
	msleep(50);
	mhl_i2c_reg_modify(TX_PAGE_3, 0x0015, BIT6, 0x00);
	mhl_i2c_reg_modify(TX_PAGE_3, 0x0010, BIT0, BIT0);
}
Beispiel #18
0
static void init_cbus_regs(void)
{
	uint8_t		regval;

	/* Increase DDC translation layer timer*/
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0007, 0xF2);
	/* Drive High Time */
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0036, 0x03);
	/* Use programmed timing */
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0039, 0x30);
	/* CBUS Drive Strength */
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0040, 0x03);
	/*
	 * Write initial default settings
	 * to devcap regs: default settings
	 */
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0080 | DEVCAP_OFFSET_DEV_STATE,
		DEVCAP_VAL_DEV_STATE);
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0080 | DEVCAP_OFFSET_MHL_VERSION,
		DEVCAP_VAL_MHL_VERSION);
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0080 | DEVCAP_OFFSET_DEV_CAT,
		DEVCAP_VAL_DEV_CAT);
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0080 | DEVCAP_OFFSET_ADOPTER_ID_H,
		DEVCAP_VAL_ADOPTER_ID_H);
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0080 | DEVCAP_OFFSET_ADOPTER_ID_L,
		DEVCAP_VAL_ADOPTER_ID_L);
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0080 | DEVCAP_OFFSET_VID_LINK_MODE,
		DEVCAP_VAL_VID_LINK_MODE);
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0080 | DEVCAP_OFFSET_AUD_LINK_MODE,
		DEVCAP_VAL_AUD_LINK_MODE);
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0080 | DEVCAP_OFFSET_VIDEO_TYPE,
		DEVCAP_VAL_VIDEO_TYPE);
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0080 | DEVCAP_OFFSET_LOG_DEV_MAP,
		DEVCAP_VAL_LOG_DEV_MAP);
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0080 | DEVCAP_OFFSET_BANDWIDTH,
		DEVCAP_VAL_BANDWIDTH);
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0080 | DEVCAP_OFFSET_FEATURE_FLAG,
		DEVCAP_VAL_FEATURE_FLAG);
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0080 | DEVCAP_OFFSET_DEVICE_ID_H,
		DEVCAP_VAL_DEVICE_ID_H);
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0080 | DEVCAP_OFFSET_DEVICE_ID_L,
		DEVCAP_VAL_DEVICE_ID_L);
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0080 | DEVCAP_OFFSET_SCRATCHPAD_SIZE,
		DEVCAP_VAL_SCRATCHPAD_SIZE);
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0080 | DEVCAP_OFFSET_INT_STAT_SIZE,
		DEVCAP_VAL_INT_STAT_SIZE);
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0080 | DEVCAP_OFFSET_RESERVED,
		DEVCAP_VAL_RESERVED);

	/* Make bits 2,3 (initiator timeout) to 1,1
	 * for register CBUS_LINK_CONTROL_2
	 * REG_CBUS_LINK_CONTROL_2
	 */
	regval = mhl_i2c_reg_read(TX_PAGE_CBUS, 0x0031);
	regval = (regval | 0x0C);
	/* REG_CBUS_LINK_CONTROL_2 */
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0031, regval);
	 /* REG_MSC_TIMEOUT_LIMIT */
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0022, 0x0F);
	/* REG_CBUS_LINK_CONTROL_1 */
	mhl_i2c_reg_write(TX_PAGE_CBUS, 0x0030, 0x01);
	/* disallow vendor specific commands */
	mhl_i2c_reg_modify(TX_PAGE_CBUS, 0x002E, BIT4, BIT4);
}