static void mhl_cbus_isr(void)
{
uint8_t regval;
int req_done = FALSE;
uint8_t sub_cmd = 0x0;
uint8_t cmd_data = 0x0;
int msc_msg_recved = FALSE;
int rc = -1;
regval = mhl_i2c_reg_read(TX_PAGE_CBUS, 0x08);
if (regval == 0xff)
return;
if (regval)
mhl_i2c_reg_write(TX_PAGE_CBUS, 0x08, regval);
pr_debug("%s: CBUS_INT = %02x\n", __func__, regval);
if (regval & BIT3) {
sub_cmd = mhl_i2c_reg_read(TX_PAGE_CBUS, 0x18);
cmd_data = mhl_i2c_reg_read(TX_PAGE_CBUS, 0x19);
msc_msg_recved = TRUE;
}
if (regval & (BIT6 | BIT5 | BIT2))
mhl_cbus_process_errors(regval);
if (regval & BIT4)
req_done = TRUE;
regval = mhl_i2c_reg_read(TX_PAGE_CBUS, 0x1E);
if (regval)
mhl_i2c_reg_write(TX_PAGE_CBUS, 0x1E, regval);
pr_debug("%s: CBUS_MSC_INT2 = %02x\n", __func__, regval);
if (regval & BIT2) {
uint8_t intr;
intr = mhl_i2c_reg_read(TX_PAGE_CBUS, 0xA0);
mhl_msc_recv_set_int(0, intr);
pr_debug("%s: MHL_INT_0 = %02x\n", __func__, intr);
intr = mhl_i2c_reg_read(TX_PAGE_CBUS, 0xA1);
mhl_msc_recv_set_int(1, intr);
pr_debug("%s: MHL_INT_1 = %02x\n", __func__, intr);
mhl_i2c_reg_write(TX_PAGE_CBUS, 0xA0, 0xFF);
mhl_i2c_reg_write(TX_PAGE_CBUS, 0xA1, 0xFF);
mhl_i2c_reg_write(TX_PAGE_CBUS, 0xA2, 0xFF);
mhl_i2c_reg_write(TX_PAGE_CBUS, 0xA3, 0xFF);
}
if (regval & BIT3) {
uint8_t stat;
stat = mhl_i2c_reg_read(TX_PAGE_CBUS, 0xB0);
mhl_msc_recv_write_stat(0, stat);
pr_debug("%s: MHL_STATUS_0 = %02x\n", __func__, stat);
stat = mhl_i2c_reg_read(TX_PAGE_CBUS, 0xB1);
mhl_msc_recv_write_stat(1, stat);
pr_debug("%s: MHL_STATUS_1 = %02x\n", __func__, stat);
mhl_i2c_reg_write(TX_PAGE_CBUS, 0xB0, 0xFF);
mhl_i2c_reg_write(TX_PAGE_CBUS, 0xB1, 0xFF);
mhl_i2c_reg_write(TX_PAGE_CBUS, 0xB2, 0xFF);
mhl_i2c_reg_write(TX_PAGE_CBUS, 0xB3, 0xFF);
}
if (msc_msg_recved) {
rc = mhl_msc_recv_msc_msg(sub_cmd, cmd_data);
if (rc)
pr_err("MHL: mhl msc recv msc msg failed(%d)!\n", rc);
}
if (req_done)
complete_all(&mhl_msm_state->msc_cmd_done);
return;
}
/* MSC, RCP, RAP messages - mandatory for compliance */
static void mhl_cbus_isr(void)
{
uint8_t regval;
int req_done = FALSE;
uint8_t sub_cmd = 0x0;
uint8_t cmd_data = 0x0;
int msc_msg_recved = FALSE;
int rc = -1;
regval = mhl_i2c_reg_read(TX_PAGE_CBUS, 0x08);
if (regval == 0xff)
return;
/*
* clear all interrupts that were raised
* even if we did not process
*/
if (regval)
mhl_i2c_reg_write(TX_PAGE_CBUS, 0x08, regval);
pr_debug("%s: CBUS_INT = %02x\n", __func__, regval);
/* MSC_MSG (RCP/RAP) */
if (regval & BIT3) {
sub_cmd = mhl_i2c_reg_read(TX_PAGE_CBUS, 0x18);
cmd_data = mhl_i2c_reg_read(TX_PAGE_CBUS, 0x19);
msc_msg_recved = TRUE;
}
/* MSC_MT_ABRT/MSC_MR_ABRT/DDC_ABORT */
if (regval & (BIT6 | BIT5 | BIT2))
mhl_cbus_process_errors(regval);
/* MSC_REQ_DONE */
if (regval & BIT4)
req_done = TRUE;
/* Now look for interrupts on CBUS_MSC_INT2 */
regval = mhl_i2c_reg_read(TX_PAGE_CBUS, 0x1E);
/* clear all interrupts that were raised */
/* even if we did not process */
if (regval)
mhl_i2c_reg_write(TX_PAGE_CBUS, 0x1E, regval);
pr_debug("%s: CBUS_MSC_INT2 = %02x\n", __func__, regval);
/* received SET_INT */
if (regval & BIT2) {
uint8_t intr;
intr = mhl_i2c_reg_read(TX_PAGE_CBUS, 0xA0);
mhl_msc_recv_set_int(0, intr);
pr_debug("%s: MHL_INT_0 = %02x\n", __func__, intr);
intr = mhl_i2c_reg_read(TX_PAGE_CBUS, 0xA1);
mhl_msc_recv_set_int(1, intr);
pr_debug("%s: MHL_INT_1 = %02x\n", __func__, intr);
mhl_i2c_reg_write(TX_PAGE_CBUS, 0xA0, 0xFF);
mhl_i2c_reg_write(TX_PAGE_CBUS, 0xA1, 0xFF);
mhl_i2c_reg_write(TX_PAGE_CBUS, 0xA2, 0xFF);
mhl_i2c_reg_write(TX_PAGE_CBUS, 0xA3, 0xFF);
}
/* received WRITE_STAT */
if (regval & BIT3) {
uint8_t stat;
stat = mhl_i2c_reg_read(TX_PAGE_CBUS, 0xB0);
mhl_msc_recv_write_stat(0, stat);
pr_debug("%s: MHL_STATUS_0 = %02x\n", __func__, stat);
stat = mhl_i2c_reg_read(TX_PAGE_CBUS, 0xB1);
mhl_msc_recv_write_stat(1, stat);
pr_debug("%s: MHL_STATUS_1 = %02x\n", __func__, stat);
mhl_i2c_reg_write(TX_PAGE_CBUS, 0xB0, 0xFF);
mhl_i2c_reg_write(TX_PAGE_CBUS, 0xB1, 0xFF);
mhl_i2c_reg_write(TX_PAGE_CBUS, 0xB2, 0xFF);
mhl_i2c_reg_write(TX_PAGE_CBUS, 0xB3, 0xFF);
}
/* received MSC_MSG */
if (msc_msg_recved) {
/*mhl msc recv msc msg*/
rc = mhl_msc_recv_msc_msg(sub_cmd, cmd_data);
if (rc)
pr_err("MHL: mhl msc recv msc msg failed(%d)!\n", rc);
}
/* complete last command */
if (req_done)
complete_all(&mhl_msm_state->msc_cmd_done);
return;
}
static void mhl_cbus_isr(struct mhl_tx_ctrl *mhl_ctrl)
{
uint8_t regval;
int req_done = 0;
uint8_t sub_cmd = 0x0;
uint8_t cmd_data = 0x0;
int msc_msg_recved = 0;
int rc = -1;
struct i2c_client *client = mhl_ctrl->i2c_handle;
regval = MHL_SII_REG_NAME_RD(REG_CBUS_INTR_STATUS);
if (regval == 0xff)
return;
if (regval)
MHL_SII_REG_NAME_WR(REG_CBUS_INTR_STATUS, regval);
pr_debug("%s: CBUS_INT = %02x\n", __func__, regval);
/* MSC_MSG (RCP/RAP) */
if (regval & BIT3) {
sub_cmd = MHL_SII_REG_NAME_RD(REG_CBUS_PRI_VS_CMD);
cmd_data = MHL_SII_REG_NAME_RD(REG_CBUS_PRI_VS_DATA);
msc_msg_recved = 1;
}
/* MSC_MT_ABRT/MSC_MR_ABRT/DDC_ABORT */
if (regval & (BIT6 | BIT5 | BIT2))
mhl_sii_cbus_process_errors(client, regval);
/* MSC_REQ_DONE */
if (regval & BIT4)
req_done = 1;
/* look for interrupts on CBUS_MSC_INT2 */
regval = MHL_SII_REG_NAME_RD(REG_CBUS_MSC_INT2_STATUS);
/* clear all interrupts */
if (regval)
MHL_SII_REG_NAME_WR(REG_CBUS_MSC_INT2_STATUS, regval);
pr_debug("%s: CBUS_MSC_INT2 = %02x\n", __func__, regval);
/* received SET_INT */
if (regval & BIT2) {
uint8_t intr;
intr = MHL_SII_REG_NAME_RD(REG_CBUS_SET_INT_0);
MHL_SII_REG_NAME_WR(REG_CBUS_SET_INT_0, intr);
mhl_msc_recv_set_int(mhl_ctrl, 0, intr);
pr_debug("%s: MHL_INT_0 = %02x\n", __func__, intr);
intr = MHL_SII_REG_NAME_RD(REG_CBUS_SET_INT_1);
MHL_SII_REG_NAME_WR(REG_CBUS_SET_INT_1, intr);
mhl_msc_recv_set_int(mhl_ctrl, 1, intr);
pr_debug("%s: MHL_INT_1 = %02x\n", __func__, intr);
MHL_SII_REG_NAME_WR(REG_CBUS_SET_INT_2, 0xFF);
MHL_SII_REG_NAME_WR(REG_CBUS_SET_INT_3, 0xFF);
}
/* received WRITE_STAT */
if (regval & BIT3) {
uint8_t stat;
stat = MHL_SII_REG_NAME_RD(REG_CBUS_WRITE_STAT_0);
mhl_msc_recv_write_stat(mhl_ctrl, 0, stat);
pr_debug("%s: MHL_STATUS_0 = %02x\n", __func__, stat);
stat = MHL_SII_REG_NAME_RD(REG_CBUS_WRITE_STAT_1);
mhl_msc_recv_write_stat(mhl_ctrl, 1, stat);
pr_debug("%s: MHL_STATUS_1 = %02x\n", __func__, stat);
MHL_SII_REG_NAME_WR(REG_CBUS_WRITE_STAT_0, 0xFF);
MHL_SII_REG_NAME_WR(REG_CBUS_WRITE_STAT_1, 0xFF);
MHL_SII_REG_NAME_WR(REG_CBUS_WRITE_STAT_2, 0xFF);
MHL_SII_REG_NAME_WR(REG_CBUS_WRITE_STAT_3, 0xFF);
}
/* received MSC_MSG */
if (msc_msg_recved) {
/*mhl msc recv msc msg*/
rc = mhl_msc_recv_msc_msg(mhl_ctrl, sub_cmd, cmd_data);
if (rc)
pr_err("MHL: mhl msc recv msc msg failed(%d)!\n", rc);
}
/* complete last command */
if (req_done)
complete_all(&mhl_ctrl->msc_cmd_done);
}
