/*
* Write to a PHY register through the MII.
*/
static void
vr_mii_writereg(device_t self, int phy, int reg, int val)
{
struct vr_softc *sc = device_private(self);
CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
mii_bitbang_writereg(self, &vr_mii_bitbang_ops, phy, reg, val);
}
void
dl10019_mii_writereg(struct device *self, int phy, int reg, int val)
{
struct ne2000_softc *nsc = (void *) self;
const struct mii_bitbang_ops *ops;
ops = (nsc->sc_type == NE2000_TYPE_DL10022) ?
&dl10022_mii_bitbang_ops : &dl10019_mii_bitbang_ops;
mii_bitbang_writereg(self, ops, phy, reg, val);
}
static int
ed_miibus_writereg(device_t dev, int phy, int reg, int data)
{
struct ed_softc *sc;
uint8_t cr = 0;
sc = device_get_softc(dev);
/* See ed_miibus_readreg for details */
if (sc->chip_type == ED_CHIP_TYPE_AX88790) {
if (phy > 0x10)
return (0);
if (phy == 0x10)
ed_asic_outb(sc, ED_AX88X90_GPIO,
ED_AX88X90_GPIO_INT_PHY);
else
ed_asic_outb(sc, ED_AX88X90_GPIO, 0);
ed_asic_barrier(sc, ED_AX88X90_GPIO, 1,
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
} else if (sc->chip_type == ED_CHIP_TYPE_TC5299J) {
/* Select page 3. */
ed_nic_barrier(sc, ED_P0_CR, 1,
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
cr = ed_nic_inb(sc, ED_P0_CR);
ed_nic_outb(sc, ED_P0_CR, cr | ED_CR_PAGE_3);
ed_nic_barrier(sc, ED_P0_CR, 1,
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
}
mii_bitbang_writereg(dev, sc->mii_bitbang_ops, phy, reg, data);
if (sc->chip_type == ED_CHIP_TYPE_TC5299J) {
/* Restore prior page. */
ed_nic_outb(sc, ED_P0_CR, cr);
ed_nic_barrier(sc, ED_P0_CR, 1,
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
}
return (0);
}
void
bmac_mii_writereg(struct device *dev, int phy, int reg, int val)
{
mii_bitbang_writereg(dev, &bmac_mbo, phy, reg, val);
}
static void
ax88190_mii_writereg(device_t self, int phy, int reg, int val)
{
mii_bitbang_writereg(self, &ax88190_mii_bitbang_ops, phy, reg, val);
}
