Beispiel #1
0
int mipi_smd_oled_hd_read_dev_reg( struct msm_fb_data_type *mfd, struct msmfb_register_read *data)
{
    const int one_read_size = 4;
    const int loop_limit = 16;
    int read_pos = 0;
    int readed_size = 0;
    int data_cnt = 0;
    int i,j;


    read_target_reg[0] = (char)data->w_data[0];
    packet_size[0] = (char)data->len;


    mipi_dsi_cmds_tx(&smd_oled_hd_tx_buf, &(mipi_smd_oled_hd_packet_size_cmd), 1);

    for (j = 0; j < loop_limit; j++)
    {
        read_position[1] = read_pos;


        if ( mipi_dsi_cmds_tx(&smd_oled_hd_tx_buf, &(mipi_smd_oled_hd_read_pos_cmd), 1) < 1 )
        {
            printk(KERN_ERR "%s. mipi_dsi_cmds_tx FAILED.\n", __func__);
            return -1;
        }

        mipi_dsi_op_mode_config(DSI_CMD_MODE);
        mipi_dsi_sw_reset();

        mipi_dsi_buf_init(&smd_oled_hd_rx_buf);


        readed_size = mipi_dsi_cmds_rx(mfd, &smd_oled_hd_tx_buf, &smd_oled_hd_rx_buf, &mipi_smd_oled_hd_read_reg_cmd, one_read_size);


        for (i = 0; i < readed_size; i++, data_cnt++)
        {
            if( data_cnt < data->len )
                data->r_data[data_cnt] = smd_oled_hd_rx_buf.data[i];
        }

        mipi_dsi_sw_reset();
        mipi_dsi_op_mode_config(DSI_VIDEO_MODE);


        read_pos += readed_size;
        if( read_pos > data->len )
            break;
    }

    return 0;
}
Beispiel #2
0
static void mdp4_dsi_video_do_blt(struct msm_fb_data_type *mfd, int enable)
{
	unsigned long flag;
	int data;
	int change = 0;

	spin_lock_irqsave(&mdp_spin_lock, flag);
	if (enable && dsi_pipe->blt_addr == 0) {
		dsi_pipe->blt_addr = dsi_pipe->blt_base;
		dsi_pipe->blt_cnt = 0;
		dsi_pipe->ov_cnt = 0;
		dsi_pipe->dmap_cnt = 0;
		change++;
	} else if (enable == 0 && dsi_pipe->blt_addr) {
		dsi_pipe->blt_addr = 0;
		change++;
	}
	pr_info("[MDP4] %s: enable=%d blt_addr=%x\n", __func__, enable, (int)dsi_pipe->blt_addr);
	spin_unlock_irqrestore(&mdp_spin_lock, flag);

	if (!change)
		return;

	/*
	 * may need mutex here to sync with whom dsiable
	 * timing generator
	 */
	data = inpdw(MDP_BASE + DSI_VIDEO_BASE);
	if (data) {	/* timing generatore enabled */	
		// apply qualcomm patch for writeback side effect
		//mdp4_overlay_dsi_video_wait4event(mfd, INTR_DMA_P_DONE);	
		if (dsi_pipe->blt_addr) {
			mdp4_overlay_dsi_video_wait4event(mfd, INTR_DMA_P_DONE);
		}
		MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
		// apply qualcomm patch for writeback side effect
		//msleep(20);	/* make sure last frame is finished */
		mdelay(10);	/* make sure last frame is finished */
		mipi_dsi_controller_cfg(0);
	}
	mdp4_overlayproc_cfg(dsi_pipe);
	mdp4_overlay_dmap_xy(dsi_pipe);

	if (data) {	/* timing generatore enabled */
		// apply qualcomm patch for writeback side effect
		//MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
		//mdp4_overlay_dsi_video_wait4event(mfd, INTR_DMA_P_DONE);
		//mdp4_overlay_dsi_video_wait4event(mfd, INTR_DMA_P_DONE);
		//MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
		if (dsi_pipe->blt_addr) {
			MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
			mdp4_overlay_dsi_video_prefill(mfd);
			mdp4_overlay_dsi_video_prefill(mfd);
			MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
		}
		mipi_dsi_sw_reset();
		mipi_dsi_controller_cfg(1);
		MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
	}
}
Beispiel #3
0
static void post_reg_access(struct msm_fb_data_type *mfd,
			    enum power_state old_state)
{
	struct mipi_dsi_data *dsi_data;

	dsi_data = platform_get_drvdata(mfd->panel_pdev);

	/* This should not be needed, but without this we sometimes don't get an
	 * interrupt when transmitting the command */
	if (mfd->panel_info.mipi.mode == DSI_VIDEO_MODE) {
		mipi_dsi_op_mode_config(DSI_VIDEO_MODE);
		mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
		mipi_dsi_sw_reset();
		mipi_dsi_controller_cfg(1);
		MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
		mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
	}
	mutex_unlock(&mfd->dma->ov_mutex);

	if (dsi_data->panel_state == DEBUGFS_POWER_ON) {
		(void)panel_next_off(mfd->pdev);
		mutex_lock(&dsi_data->lock);
		dsi_data->panel_state = old_state;
		mutex_unlock(&dsi_data->lock);
	}
	mutex_unlock(&mfd->power_lock);
}
Beispiel #4
0
/*
 * make sure the MIPI_DSI_WRITEBACK_SIZE defined at boardfile
 * has enough space h * w * 3 * 2
 */
static void mdp4_dsi_video_do_blt(struct msm_fb_data_type *mfd, int enable)
{
	unsigned long flag;
	int data;
	int change = 0;

	mdp4_allocate_writeback_buf(mfd, MDP4_MIXER0);

	if (mfd->ov0_wb_buf->phys_addr == 0) {
		pr_info("%s: no blt_base assigned\n", __func__);
		return;
	}

	spin_lock_irqsave(&mdp_spin_lock, flag);
	if (enable && dsi_pipe->blt_addr == 0) {
		dsi_pipe->blt_addr = mfd->ov0_wb_buf->phys_addr;
		dsi_pipe->blt_cnt = 0;
		dsi_pipe->ov_cnt = 0;
		dsi_pipe->dmap_cnt = 0;
		mdp4_stat.blt_dsi_video++;
		change++;
	} else if (enable == 0 && dsi_pipe->blt_addr) {
		dsi_pipe->blt_addr = 0;
		change++;
	}

	pr_debug("%s: enable=%d blt_addr=%x\n", __func__,
				enable, (int)dsi_pipe->blt_addr);
	spin_unlock_irqrestore(&mdp_spin_lock, flag);

	if (!change)
		return;

	/*
	 * may need mutex here to sync with whom dsiable
	 * timing generator
	 */
	data = inpdw(MDP_BASE + DSI_VIDEO_BASE);
	data &= 0x01;
	if (data) {	/* timing generator enabled */
		mdp4_overlay_dsi_video_wait4event(mfd, INTR_DMA_P_DONE);
		MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
		msleep(20);	/* make sure last frame is finished */
		mipi_dsi_controller_cfg(0);
	}
	mdp4_overlayproc_cfg(dsi_pipe);
	mdp4_overlay_dmap_xy(dsi_pipe);

	if (data) {	/* timing generator enabled */
		if (dsi_pipe->blt_addr) {
			MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
			mdp4_overlay_dsi_video_prefill(mfd);
			mdp4_overlay_dsi_video_prefill(mfd);
			MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
		}
		mipi_dsi_sw_reset();
		mipi_dsi_controller_cfg(1);
		MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
	}
}
static void mipi_himax_panel_recover(void)
{
	mipi_dsi_sw_reset();
	if (panel_type == PANEL_ID_VIG_CHIMEI_HX) {
		PR_DISP_DEBUG("Panel type = PANEL_ID_VIG_CHIMEI_HX\n");
		mipi_dsi_cmds_tx(&himax_tx_buf, himax_CMI_video_on_cmds,
			ARRAY_SIZE(himax_CMI_video_on_cmds));
		mipi_dsi_cmds_tx(&himax_tx_buf, himax_CMI_display_on_cmds,
			ARRAY_SIZE(himax_CMI_display_on_cmds));
	} else if (panel_type == PANEL_ID_VIG_CHIMEI_HX_C25) {
		PR_DISP_DEBUG("Panel type = PANEL_ID_VIG_CHIMEI_HX_C25\n");
		mipi_dsi_cmds_tx(&himax_tx_buf, himax_CMI_video_on_c25_cmds,
			ARRAY_SIZE(himax_CMI_video_on_c25_cmds));
		mipi_dsi_cmds_tx(&himax_tx_buf, himax_CMI_display_on_cmds,
			ARRAY_SIZE(himax_CMI_display_on_cmds));
	} else if (panel_type == PANEL_ID_VIG_CHIMEI_HX_C3) {
		PR_DISP_DEBUG("Panel type = PANEL_ID_VIG_CHIMEI_HX_C3\n");
		mipi_dsi_cmds_tx(&himax_tx_buf, himax_CMI_video_on_c3_cmds,
			ARRAY_SIZE(himax_CMI_video_on_c3_cmds));
		mipi_dsi_cmds_tx(&himax_tx_buf, himax_CMI_display_on_cmds,
			ARRAY_SIZE(himax_CMI_display_on_cmds));
	} else if (panel_type == PANEL_ID_VIG_SHARP_HX_C3) {
		PR_DISP_DEBUG("Panel type = PANEL_ID_VIG_SHARP_HX_C3\n");
		mipi_dsi_cmds_tx(&himax_tx_buf, himax_video_on_c3_cmds,
			ARRAY_SIZE(himax_video_on_c3_cmds));
		mipi_dsi_cmds_tx(&himax_tx_buf, himax_display_on_cmds,
			ARRAY_SIZE(himax_display_on_cmds));
	} else if (panel_type == PANEL_ID_VIG_SHARP_HX_C25) {
		PR_DISP_DEBUG("Panel type = PANEL_ID_VIG_SHARP_HX_C25\n");
		mipi_dsi_cmds_tx(&himax_tx_buf, himax_video_on_c2_cmds,
			ARRAY_SIZE(himax_video_on_c2_cmds));
		mipi_dsi_cmds_tx(&himax_tx_buf, himax_display_on_cmds,
			ARRAY_SIZE(himax_display_on_cmds));
	} else if (panel_type == PANEL_ID_VIG_SHARP_HX_C2) {
		PR_DISP_DEBUG("Panel type = PANEL_ID_VIG_SHARP_HX_C2\n");
		mipi_dsi_cmds_tx(&himax_tx_buf, himax_video_on_c2_cmds,
			ARRAY_SIZE(himax_video_on_c2_cmds));
		mipi_dsi_cmds_tx(&himax_tx_buf, himax_display_on_cmds,
			ARRAY_SIZE(himax_display_on_cmds));
	} else {
		PR_DISP_DEBUG("Panel type = PANEL_ID_VIG_SHARP_HX\n");
		mipi_dsi_cmds_tx(&himax_tx_buf, himax_video_on_cmds,
			ARRAY_SIZE(himax_video_on_cmds));
		mipi_dsi_cmds_tx(&himax_tx_buf, himax_display_on_cmds,
			ARRAY_SIZE(himax_display_on_cmds));
	}

	if (mipi_himax_pdata && mipi_himax_pdata->shrink_pwm)
		led_pwm1[1] = mipi_himax_pdata->shrink_pwm(bl_level_prevset);
	else
		led_pwm1[1] = bl_level_prevset;
	mipi_dsi_cmds_tx(&himax_tx_buf, himax_cmd_backlight_cmds,
			ARRAY_SIZE(himax_cmd_backlight_cmds));
}
Beispiel #6
0
static  int mdp4_dsi_video_do_blt(struct msm_fb_data_type *mfd, int enable)
{
	unsigned long flag;
	unsigned int data;
	int change = 0;
	void mdp4_overlay_dsi_video_wait4dmap(struct msm_fb_data_type *mfd);

	PR_DISP_INFO("%s: enable=%d addr=%x base=%x\n", __func__, enable, (int)dsi_pipe->blt_addr, (int)dsi_pipe->blt_base);

	spin_lock_irqsave(&mdp_spin_lock, flag);
	if (enable && dsi_pipe->blt_addr == 0) {
		dsi_pipe->blt_addr = dsi_pipe->blt_base;
		change++;
	} else if (enable == 0 && dsi_pipe->blt_addr) {
		dsi_pipe->blt_addr = 0;
		change++;
	}
	dsi_pipe->blt_cnt = 0;
	spin_unlock_irqrestore(&mdp_spin_lock, flag);

	if (!change)
		return 0;

	mutex_lock(&cmdlock);
	PR_DISP_INFO("%s: start\n", __func__);
	data = inpdw(MDP_BASE + DSI_VIDEO_BASE);
	data &= 0x01;
	if (data) {		/* timing generator enabled */
		mdp4_overlay_dsi_video_wait4dmap(mfd);
		MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
		mdelay(17);	/* make sure last frame is finished */
		mipi_dsi_controller_cfg(0, 0, 0);
	}

	mdp4_overlayproc_cfg(dsi_pipe);
	mdp4_overlay_dmap_xy(dsi_pipe);

	if (data) {		/* timing generator enabled */
		MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
		mdp4_overlay_dsi_video_wait4dmap(mfd);
		mdp4_overlay_dsi_video_wait4dmap(mfd);
		MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
		mipi_dsi_sw_reset();
		mipi_dsi_controller_cfg(1, 0, 0);
		MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
	}
	PR_DISP_INFO("%s: done\n", __func__);
	mutex_unlock(&cmdlock);


	return 0;
}
int mipi_dsi_cmd_dma_tx(struct dsi_buf *tp)
{
    int len;
    long timeout;

#ifdef DSI_HOST_DEBUG
    int i;
    char *bp;

    bp = tp->data;

    PR_DISP_INFO("%s: ", __func__);
    for (i = 0; i < tp->len; i++)
        PR_DISP_INFO("%x ", *bp++);

    PR_DISP_INFO("\n");
#endif

    len = tp->len;
    len += 3;
    len &= ~0x03;	/* multipled by 4 */

    tp->dmap = dma_map_single(&dsi_dev, tp->data, len, DMA_TO_DEVICE);
    if (dma_mapping_error(&dsi_dev, tp->dmap))
        PR_DISP_ERR("%s: dmap mapp failed\n", __func__);

    INIT_COMPLETION(dsi_dma_comp);

    MIPI_OUTP(MIPI_DSI_BASE + 0x044, tp->dmap);
    MIPI_OUTP(MIPI_DSI_BASE + 0x048, len);
    wmb();
    MIPI_OUTP(MIPI_DSI_BASE + 0x08c, 0x01);	/* trigger */
    wmb();

    timeout = wait_for_completion_timeout(&dsi_dma_comp, HZ/10);

    if (!timeout) {
        u32 isr = MIPI_INP(MIPI_DSI_BASE + 0x010c);
        MIPI_OUTP(MIPI_DSI_BASE + 0x010c, isr);
        PR_DISP_ERR("%s timeout, isr=0x%08x\n", __func__, isr);
        mipi_dsi_read_status_reg();
        mipi_dsi_sw_reset();
        atomic_set(&need_soft_reset, 1);
    }

    dma_unmap_single(&dsi_dev, tp->dmap, len, DMA_TO_DEVICE);
    tp->dmap = 0;
    return tp->len;
}
Beispiel #8
0
static int mipi_samsung_oled_off(struct platform_device *pdev)
{
	struct msm_fb_data_type *mfd;
	u32 tmp;
    
    ENTER_FUNC2();
    
	mfd = platform_get_drvdata(pdev);

	if (!mfd)
		return -ENODEV;
	if (mfd->key != MFD_KEY)
		return -EINVAL;
    
	if (samsung_oled_state.disp_on == true) {
#if 0
	   	gpio_set_value_cansleep(gpio43, 0);
	  	usleep(10);
	  	gpio_set_value_cansleep(gpio43, 1);
	  	usleep(10);
		
		mipi_dsi_sw_reset();
#endif
		tmp = MIPI_INP(MIPI_DSI_BASE + 0xA8);
		tmp &= ~(1<<28);
		MIPI_OUTP(MIPI_DSI_BASE + 0xA8, tmp);
		wmb();
           
		is_sleep = FALSE;
        samsung_oled_state.disp_initialized = false;
        samsung_oled_state.disp_on = false;
	    printk("[PANTECH_LCD] power off state (oled panel).... \n");
#ifdef CONFIG_PANTECH_F_HDMI_PW_CTRL_ON_LCD
				if (!HDMI_Get_Cable_State()) {
					hdmi_autodetect_control(HDMI_PW_OFF);
					HDMI_Schedule_Control(0);
				}

#endif	

    }   
    
    EXIT_FUNC2();
	return 0;
}
static void post_reg_access(struct msm_fb_data_type *mfd)
{
	struct mipi_dsi_data *dsi_data;

	dsi_data = platform_get_drvdata(mfd->panel_pdev);

	if (mfd->panel_info.mipi.mode == DSI_VIDEO_MODE) {
		mipi_dsi_op_mode_config(DSI_VIDEO_MODE);
		mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
		mipi_dsi_sw_reset();
		mipi_dsi_controller_cfg(1);
		MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
		mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
	}
	mutex_unlock(&mfd->dma->ov_mutex);

	if (on_state)
		(void)panel_next_off(mfd->pdev);
}
void post_reg_access(struct msm_fb_data_type *mfd)
{
	struct mipi_dsi_data *dsi_data;

	dsi_data = platform_get_drvdata(mfd->panel_pdev);
	if (mfd->panel_info.mipi.mode == DSI_VIDEO_MODE) {
		mipi_dsi_op_mode_config(DSI_VIDEO_MODE);
		mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
		mipi_dsi_sw_reset();
		mipi_dsi_controller_cfg_toggle(1);
		MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
		mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
	}
	mutex_unlock(&mfd->dma->ov_mutex);
	mutex_unlock(&mfd->power_lock);
#ifdef CONFIG_FB_MSM_RECOVER_PANEL
	mutex_unlock(&mfd->nvrw_prohibit_draw);
#endif
}
static void mipi_dsi_clk_toggle(struct msm_fb_data_type *mfd)
{
	mutex_lock(&mfd->dma->ov_mutex);

	if (mfd->panel_info.mipi.mode == DSI_VIDEO_MODE) {
		mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
		MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
		mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
		mipi_dsi_controller_cfg(0);
		mipi_dsi_op_mode_config(DSI_CMD_MODE);

		mipi_dsi_op_mode_config(DSI_VIDEO_MODE);
		mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
		mipi_dsi_sw_reset();
		mipi_dsi_controller_cfg(1);
		MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
		mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
	}

	mutex_unlock(&mfd->dma->ov_mutex);
}
/*
 * make sure the MIPI_DSI_WRITEBACK_SIZE defined at boardfile
 * has enough space h * w * 3 * 2
 */
static void mdp4_dsi_video_do_blt(struct msm_fb_data_type *mfd, int enable)
{
    unsigned long flag;
    int cndx = 0;
    struct vsycn_ctrl *vctrl;
    struct mdp4_overlay_pipe *pipe;
    long long vtime;

    vctrl = &vsync_ctrl_db[cndx];
    pipe = vctrl->base_pipe;

    mdp4_allocate_writeback_buf(mfd, MDP4_MIXER0);

    if (mfd->ov0_wb_buf->write_addr == 0) {
        pr_info("%s: no blt_base assigned\n", __func__);
        return;
    }

    spin_lock_irqsave(&vctrl->spin_lock, flag);
    if (enable && pipe->ov_blt_addr == 0) {
        pipe->ov_blt_addr = mfd->ov0_wb_buf->write_addr;
        pipe->dma_blt_addr = mfd->ov0_wb_buf->read_addr;
        pipe->ov_cnt = 0;
        pipe->dmap_cnt = 0;
        vctrl->ov_koff = 0;
        vctrl->ov_done = 0;
        vctrl->blt_free = 0;
        mdp4_stat.blt_dsi_video++;
        vctrl->blt_change++;
    } else if (enable == 0 && pipe->ov_blt_addr) {
        pipe->ov_blt_addr = 0;
        pipe->dma_blt_addr =  0;
        vctrl->blt_free = 4;	/* 4 commits to free wb buf */
        vctrl->blt_change++;
    }

    pr_info("%s: changed=%d enable=%d ov_blt_addr=%x\n", __func__,
            vctrl->blt_change, enable, (int)pipe->ov_blt_addr);

    if (!vctrl->blt_change) {
        spin_unlock_irqrestore(&vctrl->spin_lock, flag);
        return;
    }

    if (vctrl->blt_ctrl == BLT_SWITCH_TG_OFF) // QC_1204
        vctrl->blt_change = 0; // QC_1204

    spin_unlock_irqrestore(&vctrl->spin_lock, flag);

    // QC_1206 - start
    if (enable && pipe->ov_blt_addr) {
        size_t blt_vm_size;
        char *blt_vm_addr;
        unsigned long ionflag = 0;
        int rc = -1;

        blt_vm_size = roundup(mfd->panel_info.xres * \
                              mfd->panel_info.yres * 3 * 2, SZ_4K);

        if (!IS_ERR_OR_NULL(mfd->iclient)) {
            rc = ion_handle_get_flags(mfd->iclient,
                                      mfd->ov0_wb_buf->ihdl,
                                      &ionflag);
            pr_err("*** %s: rc=%x\n", __func__, rc); // QC_1207

            if (!rc) {
                blt_vm_addr = (char *) ion_map_kernel(
                                  mfd->iclient,
                                  mfd->ov0_wb_buf->ihdl,
                                  ionflag);
                pr_err("*** %s: blt_vm_addr=%x\n", __func__, (unsigned int)blt_vm_addr); // QC_1207
                if (blt_vm_addr) {
                    pr_err("*** %s: Calling memset() with blt_vm_size=%d\n", __func__, blt_vm_size); // QC_1207
                    memset(blt_vm_addr, 0, blt_vm_size);
                    ion_unmap_kernel(mfd->iclient,
                                     mfd->ov0_wb_buf->ihdl);
                }
            }
        }
    }
    // QC_1206 - end

    if (vctrl->blt_ctrl == BLT_SWITCH_TG_OFF) {
        int tg_enabled;

        vctrl->blt_change = 0;
        tg_enabled = inpdw(MDP_BASE + DSI_VIDEO_BASE) & 0x01;
        if (tg_enabled) {
            vsync_irq_enable(INTR_PRIMARY_VSYNC, MDP_PRIM_VSYNC_TERM);
            mdp4_dsi_video_wait4vsync(0, &vtime);
            MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
            mdp4_dsi_video_wait4dmap_done(0);
        }
        mdp4_overlayproc_cfg(pipe);
        mdp4_overlay_dmap_xy(pipe);
        if (tg_enabled) {
            /*
            * need wait for more than 1 ms to
            * make sure dsi lanes' fifo is empty and
            * lanes in stop state befroe reset
            * controller
            */
            usleep(2000);
            mipi_dsi_sw_reset();
            MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
        }
    }
}
/*
 * make sure the MIPI_DSI_WRITEBACK_SIZE defined at boardfile
 * has enough space h * w * 3 * 2
 */
static void mdp4_dsi_video_do_blt(struct msm_fb_data_type *mfd, int enable)
{
	unsigned long flag;
	int cndx = 0;
	struct vsycn_ctrl *vctrl;
	struct mdp4_overlay_pipe *pipe;

	vctrl = &vsync_ctrl_db[cndx];
	pipe = vctrl->base_pipe;

	mdp4_allocate_writeback_buf(mfd, MDP4_MIXER0);

	if (mfd->ov0_wb_buf->write_addr == 0) {
		pr_info("%s: no blt_base assigned\n", __func__);
		return;
	}

	spin_lock_irqsave(&vctrl->spin_lock, flag);
	if (enable && pipe->ov_blt_addr == 0) {
		pipe->ov_blt_addr = mfd->ov0_wb_buf->write_addr;
		pipe->dma_blt_addr = mfd->ov0_wb_buf->read_addr;
		pipe->ov_cnt = 0;
		pipe->dmap_cnt = 0;
		vctrl->ov_koff = 0;
		vctrl->ov_done = 0;
		vctrl->blt_free = 0;
		mdp4_stat.blt_dsi_video++;
		vctrl->blt_change++;
	} else if (enable == 0 && pipe->ov_blt_addr) {
		pipe->ov_blt_addr = 0;
		pipe->dma_blt_addr =  0;
		vctrl->blt_free = 4;	/* 4 commits to free wb buf */
		vctrl->blt_change++;
	}

	pr_info("%s: changed=%d enable=%d ov_blt_addr=%x\n", __func__,
		vctrl->blt_change, enable, (int)pipe->ov_blt_addr);

	if (!vctrl->blt_change) {
		spin_unlock_irqrestore(&vctrl->spin_lock, flag);
		return;
	}
	spin_unlock_irqrestore(&vctrl->spin_lock, flag);

	if (vctrl->blt_ctrl == OVERLAY_BLT_SWITCH_TG_OFF) {
		int tg_enabled;

		pr_info("%s: blt enabled by switching TG off\n", __func__);
		vctrl->blt_change = 0;
		tg_enabled = inpdw(MDP_BASE + DSI_VIDEO_BASE) & 0x01;
		if (tg_enabled) {
			mdp4_dsi_video_wait4vsync(cndx);
			MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
			mdp4_dsi_video_wait4dmap_done(0);
		}
		mdp4_overlayproc_cfg(pipe);
		mdp4_overlay_dmap_xy(pipe);
		if (pipe->ov_blt_addr) {
			mdp4_dsi_video_blt_ov_update(pipe);
			pipe->ov_cnt++;
			/* Prefill one frame */
			vsync_irq_enable(INTR_OVERLAY0_DONE,
						MDP_OVERLAY0_TERM);
			/* kickoff overlay0 engine */
			mdp4_stat.kickoff_ov0++;
			vctrl->ov_koff++;	/* make up for prefill */
			outpdw(MDP_BASE + 0x0004, 0);
		}
		if (tg_enabled) {
			/*
			 * need wait for more than 1 ms to
			 * make sure lanes' fifo is empty and
			 * lanes in stop state befroe reset
			 * controller
			 */
			usleep(2000);
			mipi_dsi_sw_reset();
			MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
		}
	}
}
/*
 * make sure the MIPI_DSI_WRITEBACK_SIZE defined at boardfile
 * has enough space h * w * 3 * 2
 */
static void mdp4_dsi_video_do_blt(struct msm_fb_data_type *mfd, int enable)
{
	unsigned long flag;
	int cndx = 0;
	struct vsycn_ctrl *vctrl;
	struct mdp4_overlay_pipe *pipe;

	vctrl = &vsync_ctrl_db[cndx];
	pipe = vctrl->base_pipe;

	mdp4_allocate_writeback_buf(mfd, MDP4_MIXER0);

	if (mfd->ov0_wb_buf->write_addr == 0) {
		pr_info("%s: no blt_base assigned\n", __func__);
		return;
	}

	spin_lock_irqsave(&vctrl->spin_lock, flag);
	if (enable && pipe->ov_blt_addr == 0) {
		pipe->ov_blt_addr = mfd->ov0_wb_buf->write_addr;
		pipe->dma_blt_addr = mfd->ov0_wb_buf->read_addr;
		pipe->ov_cnt = 0;
		pipe->dmap_cnt = 0;
		vctrl->ov_koff = 0;
		vctrl->ov_done = 0;
		vctrl->blt_free = 0;
		mdp4_stat.blt_dsi_video++;
		vctrl->blt_change++;
	} else if (enable == 0 && pipe->ov_blt_addr) {
		pipe->ov_blt_addr = 0;
		pipe->dma_blt_addr =  0;
		vctrl->blt_free = 4;	/* 4 commits to free wb buf */
		vctrl->blt_change++;
	}

	pr_info("%s: changed=%d enable=%d ov_blt_addr=%x\n", __func__,
		vctrl->blt_change, enable, (int)pipe->ov_blt_addr);

	if (!vctrl->blt_change) {
		spin_unlock_irqrestore(&vctrl->spin_lock, flag);
		return;
	}

	spin_unlock_irqrestore(&vctrl->spin_lock, flag);

	if (mdp_ov0_blt_ctl == MDP4_BLT_SWITCH_TG_OFF) {
		int tg_enabled;
		long long  vtime;
		tg_enabled = inpdw(MDP_BASE + DSI_VIDEO_BASE) & 0x01;
		if (tg_enabled) {
			mdp4_dsi_video_wait4vsync(0, &vtime);
			MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
			mdp4_dsi_video_wait4dmap_done(0);
		}
		mdp4_overlayproc_cfg(pipe);
		mdp4_overlay_dmap_xy(pipe);
		vctrl->blt_change = 0;
		if (tg_enabled) {
			mipi_dsi_sw_reset();
			MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
		}
	}
}
Beispiel #15
0
/*
 * make sure the MIPI_DSI_WRITEBACK_SIZE defined at boardfile
 * has enough space h * w * 3 * 2
 */
static void mdp4_dsi_video_do_blt(struct msm_fb_data_type *mfd, int enable)
{
    unsigned long flag;
    int cndx = 0;
    struct vsycn_ctrl *vctrl;
    struct mdp4_overlay_pipe *pipe;


    vctrl = &vsync_ctrl_db[cndx];
    pipe = vctrl->base_pipe;

    mdp4_allocate_writeback_buf(mfd, MDP4_MIXER0);

    if (mfd->ov0_wb_buf->write_addr == 0) {
        pr_info("%s: no blt_base assigned\n", __func__);
        return;
    }
#ifdef BLT_MODE_CHANGE_ISSUE
    wake_lock(&blt_mode_perf_up);
#endif
    spin_lock_irqsave(&vctrl->spin_lock, flag);
    if (enable && pipe->ov_blt_addr == 0) {
        pipe->ov_blt_addr = mfd->ov0_wb_buf->write_addr;
        pipe->dma_blt_addr = mfd->ov0_wb_buf->read_addr;
        pipe->ov_cnt = 0;
        pipe->dmap_cnt = 0;
        vctrl->ov_koff = 0;
        vctrl->ov_done = 0;
        vctrl->blt_free = 0;
        mdp4_stat.blt_dsi_video++;
        vctrl->blt_change++;
    } else if (enable == 0 && pipe->ov_blt_addr) {
        pipe->ov_blt_addr = 0;
        pipe->dma_blt_addr =  0;
        vctrl->blt_free = 4;	/* 4 commits to free wb buf */
        vctrl->blt_change++;
    }

    __DLOG__( vctrl->blt_change, enable, (int)pipe->ov_blt_addr);

    pr_info("%s: changed=%d enable=%d ov_blt_addr=%x\n", __func__,
            vctrl->blt_change, enable, (int)pipe->ov_blt_addr);

    if (!vctrl->blt_change) {
        spin_unlock_irqrestore(&vctrl->spin_lock, flag);
#ifdef BLT_MODE_CHANGE_ISSUE
        wake_unlock(&blt_mode_perf_up);
#endif
        return;
    }
    spin_unlock_irqrestore(&vctrl->spin_lock, flag);

    if (vctrl->blt_ctrl == BLT_SWITCH_TG_OFF) {
        int tg_enabled;

        vctrl->blt_change = 0;
        tg_enabled = inpdw(MDP_BASE + DSI_VIDEO_BASE) & 0x01;
        if (tg_enabled) {
            mdp4_dsi_video_wait4vsync(cndx);
            MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
            mdp4_dsi_video_wait4dmap_done(0);
        }
        mdp4_overlayproc_cfg(pipe);
        mdp4_overlay_dmap_xy(pipe);
        if (tg_enabled) {
            /*
            * need wait for more than 1 ms to
            * make sure dsi lanes' fifo is empty and
            * lanes in stop state befroe reset
            * controller
            */
            usleep(2000);
            mipi_dsi_sw_reset();
            MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
        }
    }
}
Beispiel #16
0
/*
 * make sure the MIPI_DSI_WRITEBACK_SIZE defined at boardfile
 * has enough space h * w * 3 * 2
 */
static void mdp4_dsi_video_do_blt(struct msm_fb_data_type *mfd, int enable)
{
	unsigned long flag;
	int data;
	int change = 0;

	mdp4_allocate_writeback_buf(mfd, MDP4_MIXER0);

	if (mfd->ov0_wb_buf->phys_addr == 0) {
		pr_info("%s: no blt_base assigned\n", __func__);
		return;
	}

	spin_lock_irqsave(&mdp_spin_lock, flag);
	if (enable && dsi_pipe->blt_addr == 0) {
		dsi_pipe->blt_addr = mfd->ov0_wb_buf->phys_addr;
		dsi_pipe->blt_cnt = 0;
		dsi_pipe->ov_cnt = 0;
		dsi_pipe->dmap_cnt = 0;
		mdp4_stat.blt_dsi_video++;
		change++;
	} else if (enable == 0 && dsi_pipe->blt_addr) {
		dsi_pipe->blt_addr = 0;
		change++;
	}

	if (!change) {
		spin_unlock_irqrestore(&mdp_spin_lock, flag);
		return;
	}

	pr_debug("%s: enable=%d blt_addr=%x\n", __func__,
			enable, (int)dsi_pipe->blt_addr);
	blt_cfg_changed = 1;

#if defined (LGE_BLT_LOCKUP_WR)
	blt_ent++;
#endif
	spin_unlock_irqrestore(&mdp_spin_lock, flag);


	/*
	 * may need mutex here to sync with whom dsiable
	 * timing generator
	 */
	data = inpdw(MDP_BASE + DSI_VIDEO_BASE);
	data &= 0x01;
	if (data) {	/* timing generator enabled */
		mdp4_overlay_dsi_video_wait4event(mfd, INTR_DMA_P_DONE);
		mdp4_overlay_dsi_video_wait4event(mfd, INTR_PRIMARY_VSYNC);
	}

#if 0 /* removed by MSM8960AAAAANLYA1049A */
	if (data) {	/* timing generator enabled */
		if (dsi_pipe->blt_addr) {
			MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
			mdp4_overlay_dsi_video_prefill(mfd);
			mdp4_overlay_dsi_video_prefill(mfd);
			MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
		}
		mipi_dsi_sw_reset();
		mipi_dsi_controller_cfg(1);
		MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
	}
#endif
}
/*
 * make sure the MIPI_DSI_WRITEBACK_SIZE defined at boardfile
 * has enough space h * w * 3 * 2
 */
static void mdp4_dsi_video_do_blt(struct msm_fb_data_type *mfd, int enable)
{
	unsigned long flag;
	int cndx = 0;
	struct vsycn_ctrl *vctrl;
	struct mdp4_overlay_pipe *pipe;

	vctrl = &vsync_ctrl_db[cndx];
	pipe = vctrl->base_pipe;

	mdp4_allocate_writeback_buf(mfd, MDP4_MIXER0);

	if (mfd->ov0_wb_buf->write_addr == 0) {
		pr_info("%s: no blt_base assigned\n", __func__);
		return;
	}

	spin_lock_irqsave(&vctrl->spin_lock, flag);
	if (enable && pipe->ov_blt_addr == 0) {
		pipe->ov_blt_addr = mfd->ov0_wb_buf->write_addr;
		pipe->dma_blt_addr = mfd->ov0_wb_buf->read_addr;
		pipe->ov_cnt = 0;
		pipe->dmap_cnt = 0;
		vctrl->ov_koff = 0;
		vctrl->ov_done = 0;
		vctrl->blt_free = 0;
		mdp4_stat.blt_dsi_video++;
		vctrl->blt_change++;
	} else if (enable == 0 && pipe->ov_blt_addr) {
		pipe->ov_blt_addr = 0;
		pipe->dma_blt_addr =  0;
		vctrl->blt_free = 4;	/* 4 commits to free wb buf */
		vctrl->blt_change++;
	}

	pr_info("%s: changed=%d enable=%d ov_blt_addr=%x\n", __func__,
		vctrl->blt_change, enable, (int)pipe->ov_blt_addr);

	if (!vctrl->blt_change) {
		spin_unlock_irqrestore(&vctrl->spin_lock, flag);
		return;
	}

	spin_unlock_irqrestore(&vctrl->spin_lock, flag);

	if (mdp_ov0_blt_ctl == MDP4_BLT_SWITCH_TG_OFF) {
		int tg_enabled;
		pr_debug("%s: blt enabled by switching TG off\n", __func__);
		tg_enabled = inpdw(MDP_BASE + DSI_VIDEO_BASE) & 0x01;
		if (tg_enabled) {
			mdp4_dsi_video_wait4dmap_done(0);
			MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
			msleep(20);
		}
		mdp4_overlayproc_cfg(pipe);
		mdp4_overlay_dmap_xy(pipe);
		if (tg_enabled) {
			if (pipe->ov_blt_addr) {
				spin_lock_irqsave(&vctrl->spin_lock, flag);
				pipe->ov_cnt++;
				vctrl->ov_koff++;
				/* kickoff overlay engine */
				mdp4_stat.kickoff_ov0++;
				INIT_COMPLETION(vctrl->ov_comp);
				vsync_irq_enable(INTR_OVERLAY0_DONE, MDP_OVERLAY0_TERM);
				outpdw(MDP_BASE + 0x0004, 0);
				spin_unlock_irqrestore(&vctrl->spin_lock, flag);
				mdp4_dsi_video_wait4ov(0);
			}
			mipi_dsi_sw_reset();
			MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
		}
		vctrl->blt_change = 0;
	}
}