/**
* Open controller instance
* - Check if driver is compatible with core version
* - Check if struct is not NULL
* - Bring up PHY for any transmissions in low power
* - Bring up controller and perform initial configuration
* @param instance pointer to structure holding the DSI Host core information
* @return dsih_error_t
* @note this function must be called before any other function in this API
*/
dsih_error_t mipi_dsih_open(dsih_ctrl_t * instance)
{
dsih_error_t err = OK;
uint32_t version = 0;
int i = 0;
if (instance == 0)
{
return ERR_DSI_INVALID_INSTANCE;
}
else if ((instance->core_read_function == 0) || (instance->core_write_function == 0))
{
return ERR_DSI_INVALID_IO;
}
/* sam
else if (instance->status == INITIALIZED)
{
return ERR_DSI_INVALID_INSTANCE;
}
else if (mipi_dsih_dphy_open(&(instance->phy_instance)))
{
return ERR_DSI_PHY_INVALID;
}
*/
else
{
instance->status = NOT_INITIALIZED;
version = mipi_dsih_hal_get_version(instance);
for (i = 0; i < mipi_dsih_no_of_versions; i++)
{
if (version == mipi_dsih_supported_versions[i])
{
break;
}
}
/* no matching supported version has been found*/
if (i >= mipi_dsih_no_of_versions)
{
if (instance->log_info != 0)
{
instance->log_info("driver does not with this core version 0x%lX", version);
}
return ERR_DSI_CORE_INCOMPATIBLE;
}
}
//mipi_dsih_hal_power(instance, 1);
mipi_dsih_hal_dpi_color_mode_pol(instance, !instance->color_mode_polarity);
mipi_dsih_hal_dpi_shut_down_pol(instance, !instance->shut_down_polarity);
err = mipi_dsih_phy_hs2lp_config(instance, instance->max_hs_to_lp_cycles);
err |= mipi_dsih_phy_lp2hs_config(instance, instance->max_lp_to_hs_cycles);
err |= mipi_dsih_phy_bta_time(instance, instance->max_bta_cycles);
if (err)
{
return ERR_DSI_OVERFLOW;
}
/* by default, return to LP during ALL, unless otherwise specified*/
mipi_dsih_hal_dpi_lp_during_hfp(instance, 1);
mipi_dsih_hal_dpi_lp_during_hbp(instance, 1);
mipi_dsih_hal_dpi_lp_during_vactive(instance, 1);
mipi_dsih_hal_dpi_lp_during_vfp(instance, 1);
mipi_dsih_hal_dpi_lp_during_vbp(instance, 1);
mipi_dsih_hal_dpi_lp_during_vsync(instance, 1);
/* by default, all commands are sent in LP */
mipi_dsih_hal_dcs_wr_tx_type(instance, 0, 1);
mipi_dsih_hal_dcs_wr_tx_type(instance, 1, 1);
mipi_dsih_hal_dcs_wr_tx_type(instance, 3, 1); /* long packet*/
mipi_dsih_hal_dcs_rd_tx_type(instance, 0, 1);
mipi_dsih_hal_gen_wr_tx_type(instance, 0, 1);
mipi_dsih_hal_gen_wr_tx_type(instance, 1, 1);
mipi_dsih_hal_gen_wr_tx_type(instance, 2, 1);
mipi_dsih_hal_gen_wr_tx_type(instance, 3, 1); /* long packet*/
mipi_dsih_hal_gen_rd_tx_type(instance, 0, 1);
mipi_dsih_hal_gen_rd_tx_type(instance, 1, 1);
mipi_dsih_hal_gen_rd_tx_type(instance, 2, 1);
/* by default, RX_VC = 0, NO EOTp, EOTn, BTA, ECC rx and CRC rx */
mipi_dsih_hal_gen_rd_vc(instance, 0);
mipi_dsih_hal_gen_eotp_rx_en(instance, 0);
mipi_dsih_hal_gen_eotp_tx_en(instance, 0);
mipi_dsih_hal_bta_en(instance, 0);
mipi_dsih_hal_gen_ecc_rx_en(instance, 0);
mipi_dsih_hal_gen_crc_rx_en(instance, 0);
instance->status = INITIALIZED;
//sam :
mipi_dsih_ecc_rx(instance ,1);
mipi_dsih_peripheral_ack(instance, 1);
mipi_dsih_tear_effect_ack(instance, 1);
mipi_dsih_hal_max_rd_size_tx_type(instance, 1);
ginstance = instance;
return OK;
}
static int32_t dsih_init(struct panel_spec *panel)
{
dsih_error_t result = OK;
dsih_ctrl_t* dsi_instance = &(autotst_dsi_ctx.dsi_inst);
dphy_t *phy = &(dsi_instance->phy_instance);
struct info_mipi * mipi = panel->info.mipi;
int i = 0;
#ifdef FB_DSIH_VERSION_1P21A
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_INT_MSK0, 0x1fffff);
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_INT_MSK1, 0x3ffff);
#else
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_ERROR_MSK0, 0x1fffff);
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_ERROR_MSK1, 0x3ffff);
#endif
if(SPRDFB_MIPI_MODE_CMD == mipi->work_mode){
dsi_edpi_init();
}
#ifndef FB_DSIH_VERSION_1P21A
dsi_instance->phy_feq = panel->info.mipi->phy_feq;
#endif
result = mipi_dsih_open(dsi_instance);
if(OK != result){
printk(KERN_ERR "autotst_dsi: [%s]: mipi_dsih_open fail (%d)!\n", __FUNCTION__, result);
autotst_dsi_ctx.status = 1;
return -1;
}
result = mipi_dsih_dphy_configure(phy, mipi->lan_number, mipi->phy_feq);
if(OK != result){
printk(KERN_ERR "autotst_dsi: [%s]: mipi_dsih_dphy_configure fail (%d)!\n", __FUNCTION__, result);
autotst_dsi_ctx.status = 1;
return -1;
}
while(5 != (dsi_core_read_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_PHY_STATUS) & 5)){
if(0x0 == ++i%500000){
printk("autotst_dsi: [%s] warning: busy waiting!\n", __FUNCTION__);
}
}
if(SPRDFB_MIPI_MODE_CMD == mipi->work_mode){
dsi_edpi_setbuswidth(mipi);
}
result = mipi_dsih_enable_rx(dsi_instance, 1);
if(OK != result){
printk(KERN_ERR "autotst_dsi: [%s]: mipi_dsih_enable_rx fail (%d)!\n", __FUNCTION__, result);
autotst_dsi_ctx.status = 1;
return -1;
}
result = mipi_dsih_ecc_rx(dsi_instance, 1);
if(OK != result){
printk(KERN_ERR "autotst_dsi: [%s]: mipi_dsih_ecc_rx fail (%d)!\n", __FUNCTION__, result);
autotst_dsi_ctx.status = 1;
return -1;
}
result = mipi_dsih_eotp_rx(dsi_instance, 1);
if(OK != result){
printk(KERN_ERR "autotst_dsi: [%s]: mipi_dsih_eotp_rx fail (%d)!\n", __FUNCTION__, result);
autotst_dsi_ctx.status = 1;
return -1;
}
result = mipi_dsih_eotp_tx(dsi_instance, 1);
if(OK != result){
printk(KERN_ERR "autotst_dsi: [%s]: mipi_dsih_eotp_tx fail (%d)!\n", __FUNCTION__, result);
autotst_dsi_ctx.status = 1;
return -1;
}
if(SPRDFB_MIPI_MODE_VIDEO == mipi->work_mode){
dsi_dpi_init(panel);
}
#ifdef FB_DSIH_VERSION_1P21A
mipi_dsih_dphy_enable_nc_clk(&(dsi_instance->phy_instance), false);
#endif
autotst_dsi_ctx.status = 0;
return 0;
}
int32_t sprdfb_dsi_init(struct sprdfb_device *dev)
{
dsih_error_t result = OK;
dsih_ctrl_t* dsi_instance = &(dsi_ctx.dsi_inst);
dphy_t *phy = &(dsi_instance->phy_instance);
struct info_mipi * mipi = dev->panel->info.mipi;
__raw_bits_or((1<<0), 0x2090021c); //enable dphy
FB_PRINT("sprdfb:[%s]\n", __FUNCTION__);
dsi_early_int();
phy->address = DSI_CTL_BEGIN;
phy->core_read_function = dsi_core_read_function;
phy->core_write_function = dsi_core_write_function;
phy->log_error = dsi_log_error;
phy->log_info = NULL;
phy->reference_freq = DSI_PHY_REF_CLOCK;
dsi_instance->address = DSI_CTL_BEGIN;
dsi_instance->color_mode_polarity =mipi->color_mode_pol;
dsi_instance->shut_down_polarity = mipi->shut_down_pol;
dsi_instance->core_read_function = dsi_core_read_function;
dsi_instance->core_write_function = dsi_core_write_function;
dsi_instance->log_error = dsi_log_error;
dsi_instance->log_info = NULL;
/*in our rtl implementation, this is max rd time, not bta time and use 15bits*/
dsi_instance->max_bta_cycles = 0x6000;//10;
dsi_instance->max_hs_to_lp_cycles = 4;//110;
dsi_instance->max_lp_to_hs_cycles = 15;//10;
dsi_instance->max_lanes = mipi->lan_number;
if(SPRDFB_MIPI_MODE_CMD == mipi->work_mode){
dsi_edpi_init();
}/*else{
dsi_dpi_init(dev->panel);
}*/
/*
result = mipi_dsih_unregister_all_events(dsi_instance);
if(OK != result){
FB_PRINT("sprdfb: [%s]: mipi_dsih_unregister_all_events fail (%d)!\n", __FUNCTION__, result);
return -1;
}
*/
dsi_core_write_function(DSI_CTL_BEGIN, R_DSI_HOST_ERROR_MSK0, 0x1fffff);
dsi_core_write_function(DSI_CTL_BEGIN, R_DSI_HOST_ERROR_MSK1, 0x3ffff);
result = mipi_dsih_open(dsi_instance);
if(OK != result){
FB_PRINT("sprdfb: [%s]: mipi_dsih_open fail (%d)!\n", __FUNCTION__, result);
return -1;
}
result = mipi_dsih_dphy_configure(phy, mipi->lan_number, mipi->phy_feq);
if(OK != result){
FB_PRINT("sprdfb: [%s]: mipi_dsih_dphy_configure fail (%d)!\n", __FUNCTION__, result);
return -1;
}
while(5 != (dsi_core_read_function(DSI_CTL_BEGIN, R_DSI_HOST_PHY_STATUS) & 5));
if(SPRDFB_MIPI_MODE_CMD == mipi->work_mode){
dsi_edpi_setbuswidth(mipi);
}
result = mipi_dsih_enable_rx(dsi_instance, 1);
if(OK != result){
FB_PRINT("sprdfb: [%s]: mipi_dsih_enable_rx fail (%d)!\n", __FUNCTION__, result);
return -1;
}
result = mipi_dsih_ecc_rx(dsi_instance, 1);
if(OK != result){
FB_PRINT("sprdfb: [%s]: mipi_dsih_ecc_rx fail (%d)!\n", __FUNCTION__, result);
return -1;
}
result = mipi_dsih_eotp_rx(dsi_instance, 1);
if(OK != result){
FB_PRINT("sprdfb: [%s]: mipi_dsih_eotp_rx fail (%d)!\n", __FUNCTION__, result);
return -1;
}
result = mipi_dsih_eotp_tx(dsi_instance, 1);
if(OK != result){
FB_PRINT("sprdfb: [%s]: mipi_dsih_eotp_tx fail (%d)!\n", __FUNCTION__, result);
return -1;
}
if(SPRDFB_MIPI_MODE_VIDEO == mipi->work_mode){
dsi_dpi_init(dev->panel);
}
return 0;
}
int32_t sprdfb_dsi_init(struct sprdfb_device *dev)
{
dsih_error_t result = OK;
dsih_ctrl_t* dsi_instance = &(dsi_ctx.dsi_inst);
dphy_t *phy = &(dsi_instance->phy_instance);
struct info_mipi * mipi = dev->panel->info.mipi;
bool resume = false;
pr_debug(KERN_INFO "sprdfb:[%s]\n", __FUNCTION__);
if(dev->panel_ready && dsi_ctx.is_inited){
resume = true;
}
if(dev->panel_ready){
dsi_ctx.is_inited = true;
}else{
dsi_early_int();
}
phy->address = SPRD_MIPI_DSIC_BASE;
phy->core_read_function = dsi_core_read_function;
phy->core_write_function = dsi_core_write_function;
phy->log_error = dsi_log_error;
phy->log_info = NULL;
phy->reference_freq = DSI_PHY_REF_CLOCK;
dsi_instance->address = SPRD_MIPI_DSIC_BASE;
dsi_instance->color_mode_polarity =mipi->color_mode_pol;
dsi_instance->shut_down_polarity = mipi->shut_down_pol;
dsi_instance->core_read_function = dsi_core_read_function;
dsi_instance->core_write_function = dsi_core_write_function;
dsi_instance->log_error = dsi_log_error;
dsi_instance->log_info = NULL;
/*in our rtl implementation, this is max rd time, not bta time and use 15bits*/
dsi_instance->max_bta_cycles = 0x6000;//10;
dsi_instance->max_hs_to_lp_cycles = 4;//110;
dsi_instance->max_lp_to_hs_cycles = 15;//10;
dsi_instance->max_lanes = mipi->lan_number;
if(dev->panel_ready && !resume){
printk(KERN_INFO "sprdfb:[%s]: dsi has alread initialized\n", __FUNCTION__);
dsi_instance->status = INITIALIZED;
return 0;
}
if(SPRDFB_MIPI_MODE_CMD == mipi->work_mode){
dsi_edpi_init();
}/*else{
dsi_dpi_init(dev->panel);
}*/
/*
result = mipi_dsih_unregister_all_events(dsi_instance);
if(OK != result){
printk(KERN_ERR "sprdfb: [%s]: mipi_dsih_unregister_all_events fail (%d)!\n", __FUNCTION__, result);
return -1;
}
*/
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_ERROR_MSK0, 0x1fffff);
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_ERROR_MSK1, 0x3ffff);
result = mipi_dsih_open(dsi_instance);
if(OK != result){
printk(KERN_ERR "sprdfb: [%s]: mipi_dsih_open fail (%d)!\n", __FUNCTION__, result);
return -1;
}
result = mipi_dsih_dphy_configure(phy, mipi->lan_number, mipi->phy_feq);
if(OK != result){
printk(KERN_ERR "sprdfb: [%s]: mipi_dsih_dphy_configure fail (%d)!\n", __FUNCTION__, result);
return -1;
}
while(5 != (dsi_core_read_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_PHY_STATUS) & 5));
if(SPRDFB_MIPI_MODE_CMD == mipi->work_mode){
dsi_edpi_setbuswidth(mipi);
}
result = mipi_dsih_enable_rx(dsi_instance, 1);
if(OK != result){
printk(KERN_ERR "sprdfb: [%s]: mipi_dsih_enable_rx fail (%d)!\n", __FUNCTION__, result);
return -1;
}
result = mipi_dsih_ecc_rx(dsi_instance, 1);
if(OK != result){
printk(KERN_ERR "sprdfb: [%s]: mipi_dsih_ecc_rx fail (%d)!\n", __FUNCTION__, result);
return -1;
}
result = mipi_dsih_eotp_rx(dsi_instance, 1);
if(OK != result){
printk(KERN_ERR "sprdfb: [%s]: mipi_dsih_eotp_rx fail (%d)!\n", __FUNCTION__, result);
return -1;
}
result = mipi_dsih_eotp_tx(dsi_instance, 1);
if(OK != result){
printk(KERN_ERR "sprdfb: [%s]: mipi_dsih_eotp_tx fail (%d)!\n", __FUNCTION__, result);
return -1;
}
if(SPRDFB_MIPI_MODE_VIDEO == mipi->work_mode){
dsi_dpi_init(dev->panel);
}
return 0;
}
int32_t sprdfb_dsih_init(struct sprdfb_device *dev)
{
dsih_error_t result = OK;
dsih_ctrl_t* dsi_instance = &(dsi_ctx.dsi_inst);
dphy_t *phy = &(dsi_instance->phy_instance);
struct info_mipi * mipi = dev->panel->info.mipi;
int i = 0;
#ifdef FB_DSIH_VERSION_1P21A
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_INT_MSK0, 0x1fffff);
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_INT_MSK1, 0x3ffff);
#else
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_ERROR_MSK0, 0x1fffff);
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_ERROR_MSK1, 0x3ffff);
#endif
if(SPRDFB_MIPI_MODE_CMD == mipi->work_mode){
dsi_edpi_init();
}/*else{
dsi_dpi_init(dev->panel);
}*/
/*
result = mipi_dsih_unregister_all_events(dsi_instance);
if(OK != result){
printk(KERN_ERR "sprdfb: [%s]: mipi_dsih_unregister_all_events fail (%d)!\n", __FUNCTION__, result);
return -1;
}
*/
// dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_ERROR_MSK0, 0x1fffff);
// dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_ERROR_MSK1, 0x3ffff);
#ifndef FB_DSIH_VERSION_1P21A
dsi_instance->phy_feq = dev->panel->info.mipi->phy_feq;
#endif
result = mipi_dsih_open(dsi_instance);
if(OK != result){
printk(KERN_ERR "sprdfb: [%s]: mipi_dsih_open fail (%d)!\n", __FUNCTION__, result);
dsi_ctx.status = 1;
return -1;
}
result = mipi_dsih_dphy_configure(phy, mipi->lan_number, mipi->phy_feq);
if(OK != result){
printk(KERN_ERR "sprdfb: [%s]: mipi_dsih_dphy_configure fail (%d)!\n", __FUNCTION__, result);
dsi_ctx.status = 1;
return -1;
}
while(5 != (dsi_core_read_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_PHY_STATUS) & 5)){
if(0x0 == ++i%500000){
dsi_print_global_config();
printk("sprdfb: [%s] warning: busy waiting!\n", __FUNCTION__);
break;
}
}
if(SPRDFB_MIPI_MODE_CMD == mipi->work_mode){
dsi_edpi_setbuswidth(mipi);
}
result = mipi_dsih_enable_rx(dsi_instance, 1);
if(OK != result){
printk(KERN_ERR "sprdfb: [%s]: mipi_dsih_enable_rx fail (%d)!\n", __FUNCTION__, result);
dsi_ctx.status = 1;
return -1;
}
result = mipi_dsih_ecc_rx(dsi_instance, 1);
if(OK != result){
printk(KERN_ERR "sprdfb: [%s]: mipi_dsih_ecc_rx fail (%d)!\n", __FUNCTION__, result);
dsi_ctx.status = 1;
return -1;
}
result = mipi_dsih_eotp_rx(dsi_instance, 1);
if(OK != result){
printk(KERN_ERR "sprdfb: [%s]: mipi_dsih_eotp_rx fail (%d)!\n", __FUNCTION__, result);
dsi_ctx.status = 1;
return -1;
}
result = mipi_dsih_eotp_tx(dsi_instance, 1);
if(OK != result){
printk(KERN_ERR "sprdfb: [%s]: mipi_dsih_eotp_tx fail (%d)!\n", __FUNCTION__, result);
dsi_ctx.status = 1;
return -1;
}
if(SPRDFB_MIPI_MODE_VIDEO == mipi->work_mode){
dsi_dpi_init(dev);
}
#ifdef FB_DSIH_VERSION_1P21A
#ifndef CONFIG_LCD_MIPI_CONTINOUS_CLK
mipi_dsih_dphy_enable_nc_clk(&(dsi_instance->phy_instance), 1);
#endif
#endif
dsi_ctx.status = 0;
return 0;
}
int32_t sprdfb_dsih_init(struct sprdfb_device *dev)
{
dsih_error_t result = OK;
dsih_ctrl_t* dsi_instance = &(dsi_ctx.dsi_inst);
dphy_t *phy = &(dsi_instance->phy_instance);
struct info_mipi * mipi = dev->panel->info.mipi;
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_ERROR_MSK0, 0x1fffff);
dsi_core_write_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_ERROR_MSK1, 0x3ffff);
if(SPRDFB_MIPI_MODE_CMD == mipi->work_mode){
dsi_edpi_init();
}
result = mipi_dsih_open(dsi_instance);
if(OK != result){
printk(KERN_ERR "[DISP] sprdfb: [%s]: mipi_dsih_open fail (%d)!\n", __FUNCTION__, result);
dsi_ctx.status = 1;
return -1;
}
result = mipi_dsih_dphy_configure(phy, mipi->lan_number, mipi->phy_feq);
if(OK != result){
printk(KERN_ERR "[DISP] sprdfb: [%s]: mipi_dsih_dphy_configure fail (%d)!\n", __FUNCTION__, result);
dsi_ctx.status = 1;
return -1;
}
while(5 != (dsi_core_read_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_PHY_STATUS) & 5));
if(SPRDFB_MIPI_MODE_CMD == mipi->work_mode){
dsi_edpi_setbuswidth(mipi);
}
result = mipi_dsih_enable_rx(dsi_instance, 1);
if(OK != result){
printk(KERN_ERR "[DISP] sprdfb: [%s]: mipi_dsih_enable_rx fail (%d)!\n", __FUNCTION__, result);
dsi_ctx.status = 1;
return -1;
}
result = mipi_dsih_ecc_rx(dsi_instance, 1);
if(OK != result){
printk(KERN_ERR "[DISP] sprdfb: [%s]: mipi_dsih_ecc_rx fail (%d)!\n", __FUNCTION__, result);
dsi_ctx.status = 1;
return -1;
}
result = mipi_dsih_eotp_rx(dsi_instance, 1);
if(OK != result){
printk(KERN_ERR "[DISP] sprdfb: [%s]: mipi_dsih_eotp_rx fail (%d)!\n", __FUNCTION__, result);
dsi_ctx.status = 1;
return -1;
}
result = mipi_dsih_eotp_tx(dsi_instance, 1);
if(OK != result){
printk(KERN_ERR "[DISP] sprdfb: [%s]: mipi_dsih_eotp_tx fail (%d)!\n", __FUNCTION__, result);
dsi_ctx.status = 1;
return -1;
}
if(SPRDFB_MIPI_MODE_VIDEO == mipi->work_mode){
dsi_dpi_init(dev);
}
dsi_ctx.status = 0;
return 0;
}